bulk connection poly resistor

Hi i am learning to do layout design in cadence and i saw one example. I have attached the schematic.

and the layout for the above schematic was given. I was able to understand everything except where for the resistor (poly resistor) in the layout they connected the drain of pmos and nmos to one terminal of the res and the other terminal of the res to the capacitor just as in schematic. And all this was fine. But then around the poly resistor an nwell was created. and then to the corner a nplus layer was formed. and from this nplus layer a metal connection was given to VDD. Why was this done??? What is this third connection for the resistor to the VDD while there is no connection in the schematic??? Its confusing. Pls help

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This is the resistor part of the layout. One terminal to the left is from drain of pmos and nmos and to the right is connection to capacitor. What about the third connection????

Likely to shield the resistor from interference coming through the substrate, or vice versa.

Check the parameters of the resistor. It may specify the bulk node is tied to VDD.

No there is nothing like that mentioned in the parameter of the resistor

Also, I have read that putting nwell under features like resistors and traces somewhat reduces parasitic capacitance to the substrate.

Hey,

You don't see that connection in some primitive cells because it's an implied connection. If you read the process document carefully it must be noted there. I'm pretty sure that there would be another instance of a similar resistor with that node left open for designer to use, because being able to bias that nwell matters in some cases.

If you are asking why the nwell is there, it's simply because this device is designed as such. It might be modelling considerations or preventing noise to couple to substrate directly.

Also check and see if you can pass LVS with and without the nwell there. It might be a requirement from the fab or it might be an additional thing. There should be a table in your process documents that would have which combination of which layers would create a device. Check to see if polyres actually requires this.

If all else fails, contact your fab, or MOSIS if you're using MOSIS. If that fails contact the US president or whatever.