Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

difference between ATPG library and verilog library

Status
Not open for further replies.
A

abc_81

Junior Member level 2
Joined
Jul 6, 2009
Messages
23
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
bangalore
Activity points
1,421
Hi,
Whats is the difference between libraried that we use for ATPG and verilog library ?

Thanks
 

There is not much difference between ATPG library and Verilog Library.
ATPG library is also made up of Verilog language. But some type of Verilog constructs can not be used in ATPG library due to ATPG tool limitation.
 

ATPG library format is dependant of the ATPG tool not necessary verilog based language.
ATPG model should defined the possible fault for the std cells.
 

Thank you. Could you please explain more on "ATPG model should defined the possible fault for the std cells".
As far as I understand, ATPG model will have the functionality of a perticular std cell. How it takes acre of defining fault in ATPG model ?
 
The std cell providers should provides this informations.
Or if you used Mentor tool, this one could extract based on GDS/CIR std cells, which generate a UDFM: user define fault model, this fault include the inside std cell routing which is usefull for "complex" std cell.
This fault has already see an improvement of 8ppm, in one of our product instead we have already 99.3% stuck coverage.
 

Hi,

Would like to raise the question again. What exactly is the difference between atpg library and verilog library??
I am looking for a generic level answer which will be easy to understand.

Thanks.
 

ATPG files describe the fault of the macros you have in your design.
Verilog files describe the functionality of the macros, with or without timing (SDF).
 

That's tool dependent.
Some one used the Verilog model to have the functionality of the cell, which is not provided by the ATPG (fault model) file.
 

rca said:
The std cell providers should provides this informations.
Or if you used Mentor tool, this one could extract based on GDS/CIR std cells, which generate a UDFM: user define fault model, this fault include the inside std cell routing which is usefull for "complex" std cell.
This fault has already see an improvement of 8ppm, in one of our product instead we have already 99.3% stuck coverage.
Click to expand...

Hi rca,

If I am not wrong, UDFM will be used in Cell Aware ATPG. My question is while defining complex std cell using UDFM aren't we increasing the number of total faults sites? Is the improvement in coverage is due to the fact that total fault sites is increased ? Also what are the other advantages of UDFM? If a gate is faulty we can deduce it from the PI/POs of the gate. Why do we need to dig into "complex" gate ? Is it the limitation of the ATPG tool library models ?

Thanks
 

It seem complex gate need a internal fault model description which could not be model by the standard model, then these internal fault model could not be catch and failed die passed the scan.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top