how to include metal line inductance in cadence/virtuoso?

after layout and DRC, LVS check and creating calibre file for post layout simulation, I realize that it doesn't seem to include the inductance caused by the metal lines.

I've read the documents that has the sheet resistance of metal lines but it doesn't have any info about inductance.

I wonder if the self/mutual inductance between metal lines are negligible. Is this why inductance is not considered?

I am currently designing an IC chip with 2.4GHz. The chip size is about 1.5mm x 0.9mm... Would even the longest metal line have considerable inductance?

The Calibre product for inductance is Calibre xL, part of the parasitic extraction group (xRC, xACT, xCalibrate, and xL). As to whether you should model inductance for your design, that depends on a bunch of things such as whether it has significant analog areas, small margins, or other reasons that you need finer-grained detail than you'd get from modeling RC alone.

Yes, you can extract all of RLCK [Resistance, Capacitance, Self-Inductance, and Mutual-Inductance] of all interconnect wires[for smaller blocks], or selective nets[for larger designs], by using Cadence QRC extraction tool. Inductance extraction is usually required for for higher frequencies - I am aware of Analog Designers doing so from 2GHz - to - 80 GHz using Cadence QRC.

Yes, Mutual Inductance is more important than self. These LK may not be negligible. The reason Inductance is not considered at times - extraction and analysis of Inductance is expensive, w.r.t. time & money, not every design can afford so, and various margins, over-design factors pays that part. However, for very high-frequency - they do LK extraction.
In most cases, they use PEEC & Ladder-network - that also includes "skin-effect" and "proximity-effect", the bad side-effect is, the result netlist size, as well as simulation runtime increases dramatically. So, there always remains a conscious tradeoff between how-much we need to extract, to get meaningful result within some specified time.
Users do not extract LK [self&mutual inductance] - over the whole chip, rather they choose selective user-region/s [RF design needs experience - to choose appropriate regions].
For a clock at 2.4GHz, a decent presence of the third harmonic [7.2 GHz] makes sense for some designers - so during s-parameter analysis, while doing frequency sweep they check both the value and phase beyond 3x the design frequency as well..