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Is there any method for interface between AXI bus and SRAM ?

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u24c02

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Hi.

I want make interface between AXI 3.0 bus and SRAM ?
but i'm not sure about how can i interfacing between both.

I have AMBA Design Kit (NIC-301).

Is there any method( or example) for interface between AXI bus and SRAM ?
 

I'm sure there is a way to interface them, I did it with AXI4. Study the bus timing and design a circuit to apply the address and data to the SRAM address/data inputs and generate the write enable from decoding the address and the valid.
 
Could you please more detail?
 

The detail is called "design".

I had to design an interface for the AXI4 to SRAM/registers/FIFO for the product. Just read the AXI spec, that's what I did.
 

So is there any needs some bridges? Or interconnections?
Bus just directly connect to sram?
 

The circuit you design is a bridge, just not an off the shelf pre-made one, instead it is a custom one. Like I said use the address and decode the upper bits to determine if you are accessing the SRAM and use the decode and the vaild strobe to generate a write pulse while applying the address and data to the SRAM. To read you have to do something similar, but in that case you need to output to the data to the AXI master and generate the valid.

I'm not going to write the code for you.
 

You can have a look at this one:

https://www.synopsys.com/dw/dwtb.php?a=sram_to_axi

With the available SRAM signals and AXI3 signals, you can write a bridge(e.g. State machine) which will handle the communication between them. Then try to simulate.
 
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