image processing histogram and ram

yupina-chan said:

hi. i have a histogram module which worked fine when simulated. now, i want to apply it in image processing. i use terasic d5m camera and after taking a snapshot, i would like to take its histogram. i have read that a ram block is needed to implement it to fpga. what i don't understand is how to do it. can you give me hints in doing this? or a diagram on input and output ports of the histogram and ram block. thanks in advance.

i have included my histogram code. will this be okay for my desired implementation?

Code:

module histogram(data_in, out1, out2, out3, out4, out5,out6,out7,out8, clk, reset);
output reg [7:0] out1;
output reg [7:0] out2;
output reg [7:0] out3;
output reg [7:0] out4;
output reg [7:0] out5;
output reg [7:0] out6;
output reg [7:0] out7;
output reg [7:0] out8;
input [7:0] data_in;
input clk;
input reset; 
 
always @ (posedge clk or negedge reset)
	begin
	if (!reset)
	begin
			out1 <= 0;
			out2 <= 0;
			out3 <= 0;
			out4 <= 0;
			out5 <= 0;
			out6 <= 0;
			out7 <= 0;
			out8 <= 0;
	end
	else
	begin
			if (data_in >= 8'b11100000)
			begin
				out8 = out8 + 1;
			end
			else if (data_in >= 8'b11000000)
			begin
				out7 = out7 + 1;
			end
			else if (data_in >= 8'b10100000)
			begin
				out6 = out6 + 1;
			end
			else if (data_in >= 8'b10000000)
			begin
				out5 = out5 + 1;
			end
			else if (data_in >= 8'b01100000)
			begin
				out4 = out4 + 1;
			end
			else if (data_in >= 8'b01000000)
			begin
				out3 = out3 + 1;
			end
			else if (data_in >= 8'b00100000)
			begin
				out2 = out2 + 1;
			end
			else if (data_in >= 8'b00000000)
			begin
				out1 = out1 + 1;
			end
	end
	end

endmodule

Click to expand...

aruipksni said:

1. you can use their (terasic) reference design blocks.
2. you need to store histograms for 3 RGB values...
3. you can then store histograms in ram block or memory (depends on you application) - you defenatly need to save
the picture in memory (SDRAM), what is already done in the refference design.

Click to expand...

yupina-chan said:

thanks for the reply. i wanna ask what do you mean by 1?

Click to expand...

yupina-chan said:

how many ram blocks will i have for an 8-bin histogram? how can the histogram count be saved into the ram block? i mean, the mem (in my code) stores it in some kind of array but in the histogram side, what port is it connected, i don't think i can have an array as an output? and how can i incorporate my histogram module to the ram block? below is a ram module i coded based on examples. please, i need some enlightenment on this.

Code:

module ram(
								CLK,
								RESET_N,
								ENABLE,
								RW_SELECT,
								ADDRESS,
								DATA_IN,
								DATA_OUT
								);
								
input					CLK;					//clock input
input					RESET_N;				//asynchronous reset (active low)
input					ENABLE;				//enable RAM operations
input					RW_SELECT;			//select read '0' or write '1'
input [7:0]			ADDRESS;				//address to read from or write to
input [7:0]			DATA_IN;				//data input
output reg [7:0]		DATA_OUT;			//data output

reg[7:0] mem[0:7];						//size:256, 8 bits


//synchronous process with asynchronous active-low reset
//if RAM enable='1' and rw_select='0'
//		data word is read from the specified address at each positive clock edge and output at data_out 
//if RAM enable='1' and rw_select='1'
//		data from data_in is written to the specified address at each positive clock edge

always @ (posedge CLK or negedge RESET_N)
begin

	if (RESET_N == 0)
	begin
			mem[ADDRESS] <= 0; 
			DATA_OUT <= 0;
	end
	else
	begin
		if (ENABLE == 1 && RW_SELECT == 0)				//read from RAM
			begin
					DATA_OUT <= mem[ADDRESS];		
			end	
		else if 	(ENABLE == 1 && RW_SELECT == 1)		//write to RAM
			begin
					mem[ADDRESS] <= DATA_IN;	
			end
	end
end

endmodule

Click to expand...

aruipksni said:

basically you don't need to use counters or array of registers, to store an histogram, you can use a dual port ram.
and thus you can use larger bins histogram then 8 -bins.

so in your case have :

------------------------
vid data 8 bit -- your 8-bin decoder -- ==> A(2..0) 3 bit address.
------------------------

so for dual port ram you can do something like :


T ------------ n ------- n+1 -------- n+2 ---
------------------------------------------------
ADD RD -----A --- A(n+1) .....
ADD WR-------------- A ------- A(n+1) ...
DATA rd-------------- H ------- H(n+1) -- ...
DATA wr ------------ H +1 ---- H(n+1) +1 -- ...

A - address.
H - histogram
n - clock number.

you can then store more histograms by manipulating the high address bits of the dpram.
=======
hist counter ===> decoder ==> address 10..4 for instance..
========

Click to expand...

yupina-chan said:

at first, i didn't really understand about this. but when i looked it up in books and in the internet. wow, i was really an idiot. i didn't think it was stated in the book i was reading a long time ago (in design for embedded image processing on fpga by donald bailey). thank you.

can i ask one more thing? i intend to apply this for histogram matching. can i do so? if you have any idea, can i ask for hints?
thank you once again.

Click to expand...

yupina-chan said:

hi. i saw a dual-port based histogram calculation block. i modified it and tried to make my own code. below is my histogram block and my code. i don't know if this is what you are implying on your reply above but i have it in dual-port ram.

Code:

//dpram
module dpram(
       q_a,
		 clk,
		 reset,
       rd_addr,
		 read,
       data_b,
       wr_addr,
		 write
		 );

input clk, reset, read, write;   
input [7:0]	rd_addr, wr_addr;     
output reg [7:0] q_a;  
input [7:0] data_b;

reg [7:0] ram[255:0];

always @(posedge clk or negedge reset)
begin
	if (!reset)
	begin
		q_a <= 0;
		ram[rd_addr] = 0;
		ram[wr_addr] = 0;
	end
	else
	begin
		if (read)
		begin
			q_a <= ram[rd_addr];
		end
		if (write)
      begin
			ram[wr_addr] <= data_b;
		end
	end
end
endmodule

//adder
module adder (c, x, clk, reset);
input [7:0] x;
input clk, reset;
output reg [7:0] c;

always @(posedge clk or negedge reset) begin
	if (!reset)
		c = 0;
	else
	begin
	c = x + 1;
	end
end
endmodule

//top
module top(
		q_a,
       clk,
		 reset,
       address,
		 read,
		 write
		 );

input clk, reset, read, write;   
input [7:0]	address;     
output [7:0] q_a;  

dpram m1(q_a, clk, reset, address, read, data_b, address, write);
adder m2(data_b, q_a, clk, reset);
endmodule

Click to expand...