Virtex_5_LX110T DDR2 SDRAM ucf and chipscope problem,

try to use ddr2 sdram on virtex_5 lx110t board. I generate the example design by using mig. Then i simulate the design with modelsim and it works. Then i wanted to see the signals on chipscope but first of all i had clock problem of trigger, as you know if there is a clock problem with trigger so it means something is problem with clock pins or clock generation. The first problem is, the ucf which is automatically generated mig and ml509_master_ucf file are not similar, here is an example,

mig36_1.ucf

NET "sys_clk_p" LOC = "H17" ; #Bank 3
NET "sys_clk_n" LOC = "H18" ; #Bank 3


ml509_master_ucf

NET SMA_DIFF_CLK_IN_N LOC="H15"; # Bank 3, Vcco=2.5V, No DCI
NET SMA_DIFF_CLK_IN_P LOC="H14"; # Bank 3, Vcco=2.5V, No DCI

so the ucf file which is generated automatically by mig is not relaible? It is nearly 1 month i am trying to run ddr2 but unfortunately i couldnt solve the problem. How can i achieve this problem? what do you prefer for me to generate the clocks and ucf file?

Kind Regards

You need to use the ml509_master.ucf pins for the DDR2. The H17 and H18 pins are PHY_RXCLK and GPIO_LED_0 respectively. This means you'll probably have to change some of the other placement constraints as they will be in the wrong location for the bank/pin selection. I suppose the MIG generated core just selected arbitrary pins when your ran it. I'm pretty sure there is a way to specify pins in MIG so you can match up the pinout of the ML509 board, but I don't recall the specifics of how to do it.

Regards

Hi ads-ee,

Thanks for answer, exactly those pins are not related to clock pins, there are some missing pins also. I can correct the pins with ml509_master.ucf, but the problem is there are other spefic notations. For example : INST "*/gen_dq[*].u_iob_dq/gen*.u_iddr_dq" TIG ;
it is impossible to correct the automatic generated ucf file with ml509_master.ucf , because there are other specific codes in ucf file.
I know what you mean when u generate the mig instead of selecting new desing, u can select pixed pinout and you can select the banks that u want to use. But still i need a ucf file(not only pin locations but also other codes written in ucf file) which is working on virtex_5_lx110t board.
I really didnt understand why xilinx mig doesnt generate the correct ucf file. At the attachemnt you can find 2 ucf files example. mig_36_1 is the file that i have generated by mig, ddr2_sdram is an reference design file https://www.xilinx.com/univ/xupv5-lx110t-refdes.htm
when you compare 2 ucf file then u can see the differences, then you can correct the pin locations, what about other ucf codes?
Any idea?

Kind Regards

grenader said:

those pins are not related to clock pins, there are some missing pins also. I can correct the pins with ml509_master.ucf, but the problem is there are other spefic notations. For example : INST "*/gen_dq[*].u_iob_dq/gen*.u_iddr_dq" TIG ;

Click to expand...

Well that INST line should have the same hierarchy in the underlying files structure of the core regardless of where you instantiate the core as it begins with "*/". Some of the lines in the MIG ucf will likely require updates to the hierarchical name so it will match the design.

grenader said:

it is impossible to correct the automatic generated ucf file with ml509_master.ucf , because there are other specific codes in ucf file.

Click to expand...

You should copy the ml509_master.ucf to a new ucf file which will be the design .ucf file. Then modify that ucf file with the lines that don't exist like that INST "*/gen_dq[*] .... TIG ; line and any timespecs.

grenader said:

I really didnt understand why xilinx mig doesnt generate the correct ucf file. At the attachemnt you can find 2 ucf files example. mig_36_1 is the file that i have generated by mig, ddr2_sdram is an reference design file https://www.xilinx.com/univ/xupv5-lx110t-refdes.htm

Click to expand...

The MIG tool is for generating memory interfaces and can be used for generating designs for more than just a Xilinx ML509 board, therefore it generates what is required to implement the design depending on whatever pin placement you give it or what it is allowed to decided to give you. As you left it for MIG to decide the precise pin locations the pin locations are all different than the ML509 FPGA/DDR2 pinout. So as I've said use the pins that are in the ml509_master.ucf, check if they are the same as your ddr2_sdram reference file. If the pinout is the same then placement information like: INST "*/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y96"; and INST "*/u_phy_calib/gen_gate[0].u_en_dqs_ff" LOC = SLICE_X0Y48; should all be transferred into your design ucf file. If the ddr2_sdram reference design was for a different board/pinout then you'll have to determine the correct ILOGIC_X#Y# placement constraints to match the pinout and the correct slice location constraints. There are more than these two examples of constraints you'll have to migrate to your design ucf file.

Regards

Hi ads-ee

Thanks alot i did the same what you said, now it works and i can see everything on chipscope fine. Just one more question, in example ddr2_sdram ucf file there are :

#INST "*/IDELAYCTRL_INST[0].u_idelayctrl" LOC=IDELAYCTRL_X0Y1;
#INST "*/IDELAYCTRL_INST[1].u_idelayctrl" LOC=IDELAYCTRL_X0Y2;
#INST "*/IDELAYCTRL_INST[2].u_idelayctrl" LOC=IDELAYCTRL_X0Y6;

andd ....


#INST "*/gen_dq[0].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y42; # AF30 X0Y22 *
#INST "*/gen_dq[1].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y43; # AK31 X0Y23
#INST "*/gen_dq[2].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y45; # AF31 X0Y25
.
.
.
.
.
#INST "*/gen_dq[62].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y138; # L25 X0Y118
#INST "*/gen_dq[63].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y139; # L24 X0Y119


codes, when i use them in my design.ucf it gives erors in translate and maping, for example when i uncomment idelay codes it gives errors on translating as :

ERROR:ConstraintSystem:58 - Constraint <INST "*/IDELAYCTRL_INST[0].u_idelayctrl"
LOC=IDELAYCTRL_X0Y1;> [mig_36_1.ucf(196)]: INST
"*/IDELAYCTRL_INST[0].u_idelayctrl" does not match any design objects.

example design rtl codes and my design rtl codes are totally same but it gives erros like this. Also in desgin there is ddr2_idelay_ctrl.v rtl codes...What should be the main reason?

what about the RLOC?

Kind Regards

Hakan

Hakan,

Those INST locations are commented out, I'm assuming they weren't commented out in the MIG ucf?

You might have to look at the synthesized design as the ERROR looks to be related to the name of the instance.

Well if you don't have the ddr2_idelay_ctrl.v instantiated then that is probably why you are getting the ERROR. That module is used for setting the I/O delays per pin, which is used for calibration purposes.

Hi,

Those codes are not comented in orginal ddr2_sdram.ucf example file. When i was writing them on eda board i wrote with (#). Maybe it confused you. I mean, when i add those codes to my design.ucf it gives erors. All rtl codes are same with example design and my design, so why there is error? In my design there is also ddr2_idelay_ctrl.v !!! Maybe it is litle bit detail but i just wondered why there is error.

Thanks for Reply