GALS and PALS codiing

I have seen these devices and have codes in the form of a text file that I am trying to figure out what they do,
it looks a bit like C code but in places I am not sure about things I'll highlight them in red and if anyone could tell
me what the highlighted item means I'd appreciate it. What I would like to do ultimately in convert this to a Xilinx CPLD.
Why do you ask - that sort of seems wasteful you say. Well not for my I have bucket loads of them that I got for two cents each.
Plus knowing what the circuitry looked like as a circuit diagram I could implement many PAL's / GAL's in one CPLD due to its higher pin count.
BTW: My comments are not there to mock the person responsible for writing the code - I believe he knew what he was doing - they simply illustrate my
utter lack of understanding and trying to interpret what is going on from that base of limited understanding

Cheers in advance to any respondents.

PARTNO xxxxxxxx-xx;
NAME U701;
DATE January 30, 1992;
REV 3 ;
DESIGNER Haynie ;
COMPANY Commodore ;
ASSEMBLY A30000 ;
LOCATION U701 ;

/************************************************************************/
/* */
/* A3000 Interrupt mixing & latch, primary bus arbitration */
/* */
/************************************************************************/
/* Allowable Target Device Types: 16R4A */
/************************************************************************/
/* Clock: 7Mhz */
/************************************************************************/
/* Free Pins: 14(Q) */
/************************************************************************/
/* HISTORY */
/* DBH Apr 5: Completely new. */
/* DBH Dec 6: Added bus arbiter stuff. */
/* DBH Jan 30: Changes to run without motherboard CPU. */
/************************************************************************/

/** Inputs **/
OK I get that this is declaring what pins are input and output but what does the !mean in front of the pin name
Active High?, Active Low?, This is a physical pin name as opposed to a programming logic name? what the pin connects to somewhere else in the board universe
Something else?
PIN 2 = !CIPL0 ; /* Chip conditioned interrupts */
PIN 3 = !CIPL1 ;
PIN 4 = !CIPL2 ;
PIN 5 = !PINT1 ; /* Bus interrupts */
PIN 6 = !PINT4 ;
PIN 7 = !PINT5 ;
PIN 8 = !PINT7 ;
PIN 9 = !INTENB ; /* Interrupt enable */
PIN 18 = !CBR ; /* Coprocessor slot bus request */
PIN 19 = !BOSS ; /* Coprocessor slot owns system */[/COLOR]

/** Outputs **/
PIN 17 = !IPL0 ; /* CPU interrupts */
PIN 16 = !IPL1 ;
PIN 15 = !IPL2 ;
PIN 12 = !BG ; /* Bus grant out to Buster */

/** Bidirectionals **/

PIN 13 = !BG30 ; /* Bus Grant from 68030 */

/** Declarations and Intermediate Variable Definitions **/

/* This sets up the different interrupt levels, as they may be
generated by Paula or the discrete interrupt lines. These
terms handle the prioritization. */

Ok the following line looks to me like its anding values together to form a mask representing something but again
the ! are throwing me off

level0 = !CIPL2 & !CIPL1 & !CIPL0 & !(PINT1 # PINT4 # PINT5 # PINT7);

Ok I've got no idea if the # line is part of the previous line starting with level1 or performing its own calculations, what does it do?
level1 = !CIPL2 & !CIPL1 & CIPL0 & !(PINT4 # PINT5 # PINT7)
# PINT1 & !(PINT4 # PINT5 # PINT7);

level2 = !CIPL2 & CIPL1 & !CIPL0 & !(PINT4 # PINT5 # PINT7);

level3 = !CIPL2 & CIPL1 & CIPL0 & !(PINT4 # PINT5 # PINT7);

level4 = CIPL2 & !CIPL1 & !CIPL0 & !(PINT5 # PINT7)
# PINT4 & !(PINT5 # PINT7);

level5 = CIPL2 & !CIPL1 & CIPL0 & !PINT7
# PINT5 & !PINT7;

level6 = CIPL2 & CIPL1 & !CIPL0 & !PINT7;

level7 = CIPL2 & CIPL1 & CIPL0
# PINT7 ;

/** Logic Equations **/

/* Here we drive the interrupt bits. */

Hmmm what is IPL2.D? is it defining some sort of structure? or is it saying do something to the IPL2 pin if so what does the .D mean
IPL2.D = level7 & INTENB
# level6 & INTENB
# level5 & INTENB if
# level4 & INTENB ;

IPL1.D = level7 & INTENB
# level6 & INTENB
# level3 & INTENB
# level2 & INTENB ;

IPL0.D = level7 & INTENB
# level5 & INTENB
# level3 & INTENB
# level1 & INTENB ;

/* This is the bus grant stuff. When the A3000 has a processor on the
motherboard, the equations looks like this:

Ok I think I get what this is trying to do but where did .OE get plucked from?, and as for BG30 I've not seen that get defined yet - what the? I swear this is just making things up as it goes along
BG = BG30 & !CBR;
BG.OE = !BOSS;

The idea behind the coprocessor slot is to turn arbitration over to the
coprocessor device if its present. This means we can't clog the '030's
arbitration mechanism. The system and coprocessor each have their own
bus request (BR*, CBR*) and bus grant acknowledge (BGACK*, BOSS*), either
of which have the desired effect on the motherboard '030. This gives the
coprocessor a separate channel, so it can get rid of the '030 and still
arbitrate the system requests. The grant line, however, isn't an input,
but in fact an output to the system. So it must really be multiplexed
rather than shared -- the '030's BG* goes to the system when it's in
charge, the coprocessor's BG* when it's in charge. The coprocessor is
clever enough to keep it's BG* in tristate until it owns the system, but
the '030 doesn't know about all this. So this PAL isolates the system
BG* from the '030's BG* when the coprocessor is in charge. In order to
prevent the system from seeing any grants while the coprocessor is
acquiring the bus, BG* only flows from BG30* when no coprocessor request is
happening.

That's a nice story, and all well and good until this PAL came along. It
proports to let you run your A3000 with no motherboard processor, while
staying compatible with existing coprocessor protocols. First, let's look
at the coprocessor protocol. The coprocessor takes over by asserting CBR*
and waiting for BG30* to be returned to it. Then it asserts BOSS* and
negates CBR*, which results in BG30* being negated. It now owns the bus
and directly deals with BR*, BG*, and BGACK* to the system just like any
'030 equivalent. Basically, without a motherboard processor, a coprocessor
device can just get up and go, not permission required. However, to fake
out coprocessor devices that deal with normal A3000s, the best thing to do
is make BG30* respond immediately to CBR*, thereby making the coprocessor
think some kind of motherboard processor is actually present. */

Not defined and now we are setting it to a value - this feels disaster worthy
BG30 = CBR;

/* This has no bearing on devices that run in sharing mode (the C= '040 board
is the only one of these I know about). There would be a problem with that
mechanism here. Basically, these devices time multiplex the system BR* line
with the Buster chip. The problem is that when such a device asserts BR*,
there's not going to be a motherboard processor around to assert BG* for
them. We could do it here if this PAL got BR* routed to it (we already
have BG*). That shouldn't be a problem in a new system, since all these
PINT* lines are obselete.

BG = BR;

*/

Oh man, this looks a lot like ABEL. It's a logic hardware description language for very low level logic, at the level of AND and OR gates. It was eventually replaced by other HDL's like Verilog and VHDL, if I recall.

OK I get that this is declaring what pins are input and output but what does the !mean in front of the pin name
Active High?, Active Low?, This is a physical pin name as opposed to a programming logic name? what the pin connects to somewhere else in the board universe
Something else?

Click to expand...

The "!" means not. So PIN 2 = !CIPL0 ; means that Pin2 will output whatever CIPL0 is, negated.

Ok the following line looks to me like its anding values together to form a mask representing something but again
the ! are throwing me off

Click to expand...

Yes, correct! "&" is the symbol for AND, # is the symbol for OR. Thus:
level0 = !CIPL2 & !CIPL1 & !CIPL0 & !(PINT1 # PINT4 # PINT5 # PINT7);
can be read as
level0 = (Not CIPL2) AND (Not CIPL1) AND (Not CIPL0) AND (Not [PINT1 OR PINT4 OR PINT5 OR PINT7])

Ok I've got no idea if the # line is part of the previous line starting with level1 or performing its own calculations, what does it do?

Click to expand...

Lines continue until a semicolon. Enters are ignored. The # is a spillover from the above line.

Hmmm what is IPL2.D? is it defining some sort of structure? or is it saying do something to the IPL2 pin if so what does the .D mean

Click to expand...

I believe the .D means a delay flip flop. I don't see the clock definition; usually it's followed by IPL2.CLK or something. However, this are specific pin chips, so they probably are running off of that top 7MHz clock in the header.

Ok I think I get what this is trying to do but where did .OE get plucked from?, and as for BG30 I've not seen that get defined yet - what the? I swear this is just making things up as it goes along

Click to expand...

Yes, it certainly feels like that the first time you look at this type of code! .OE is the output enable.

Not defined and now we are setting it to a value - this feels disaster worthy
BG30 = CBR;

Click to expand...

My best guess for this is that CBR is a pin that is being externally driven, or an internal signal. I didn't really read all the documentation, but that's my guess.

Here's a reference sheet you might find very useful:
**broken link removed**

ABEL is cute. It was my first HDL and very useful in understanding low level optimizations. That said, it can be very verbose and annoying when working with systems that are larger than a handful of equations.

Hope this helps!