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Need help in coding multiplier using shift and add method in verilog

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arpkum

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Hi all,

Please provide me some valuable inputs regarding multiplier using shift and add method in verilog.
say : multiplicand and multiplier be two inputs of 8 and 6 bits respectively.
and it should follow 2's compliment of positive numbers
Note :- 2's compliment of a positive number is the same number

Thanks
arpit
 

when you shift left a binary number it means you multiplied it by two.
and you can add the number ,n times,which n is the multiplier
coding it wouldn't be difficult
hope this helps
 
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    arpkum

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Hi Arpkum,

If any one of your operand is a constant one then there is an easy way like this:

Say if one of your multiplier operand is 11, then 11 can be represents in the power of 2 as 11 = 8 + 2 + 1 = 2^3 + 2^1 + 2^0

And if A is the other operand

Then A*11 = A*8 + A*2 + A = A*(2^3) + A*(2^1) + A*(2^0) = A with padding 3 zero's on LSB + A with padding 1 zero's on LSB + A itself
in Verilog {A, 3'b0} + {A, 1'b0} + A
in VHDL A & "000" + A & "0" + A

- - - Updated - - -

If both the operands are unknown then i think you should have a mechanism to represents any one of the operator in the power of 2 and you need to perform the above operation.
 
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    arpkum

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HI all ,
Thanks to all for your humble response, Can any body share me a piece of code regarding multiplier using shift and add method, I believe this would help me in a good way.
Thanks
arpit
 

HI shibin,
thanks for the vhdl code , can i get verilog code for the same .
Regards
Arpit
 

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