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RAM generation from CORE GEN 13.2 (Block Memory Generator 6.2)

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Hi,

I want to use a single port 32kb RAM in Virtex 5 FPGA. I obtained attached VHDL file from CORE GENERATOR in ipcore_dir folder, this file is a simulation model of the RAM. My question is, Where should I look for actual implementation file for this generated RAM, which can be synthesized with my existing project? I am using CORE GENERATOR for the first time so I am not sure how to use generated cores like that in your own design.

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  • DMEM.txt
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You use the NGC file. Include it in your synthesis.

r.b.
 
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