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true transistor layout?

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april1975

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HELLO
i want to sketch multi-m multi-finger transistor layout for an NMOS transistor. Is below picture true?
s3.png
pls hlp. how do i need to edit it?
I see in this layout, some blinking rectangles on poly with their diagonals. Is there any error?
 

Hello
No answer to my question?! pls hlp.
The uploaded picture is for a nmos2v transistor that has layed out by cadence layout. It has:
finger=5 and m=5
the gates are connected via POLY pathes.
pls tell me is it a true layout?
 

Hello,

I don't think this is a problem. I constantly got these warnings when joining the gate terminals of transistors having gate contacts on both sides.
It a warning, like the one on the schematic when 4 or more wires join on the same point.

But then again I don't see the reason to break the transistor in so many pieces.
 
Last edited:
Hello lamoun
You wrote:
But then again I don't see the reason to break the transistor in so many pieces.
Click to expand...
Do you have a better solution?
Do you say that I instance a MOS with 25 finger? Isn't it a very long trnsistor?
I'm newbie in layout and so I appreciate any direction. tnx
 
Last edited:

It is not how I would expect a fingered layout to look. Something like this is more like I would expect:

**broken link removed**

Keith
 
hello keith
do you have created drain and source pathes in differnt metal layers?
 

april1975 said:
Do you have a better solution?
Do you say that I instance a MOS with 25 finger? Isn't it a very long trnsistor?
Click to expand...

Not 25 fingers. 5 finger but with 5*W.
Same as if you stick the 5 transistors together.
This would be more compact than the layout you already have.
 
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