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[SOLVED] "signal or port name expected as actual in association element.(VSS-806)"

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hello,I want synt my vhdl code in 0.13 ,and I use design_vision to syn it.
when I wnat to analyze it,this error occured.
"signal or port name expected as actual in association element.(VSS-806)"


total_01:total_1_a port map(00,clk_internal,clr_in,L_matrix_row,length_row_i,length_row_i_pre,col_each_rowblock_ii,col_index_nonzero_01,sign_value_i(01),sign_value_i_pre(01),sign_each_row_i(01),sign_each_row_i_pre(01),index_min_i(01),index_min_i_pre(01),out_min_1_i(01),out_min_2_i(01),out_min_1_i_pre(01),out_min_2_i_pre(01),out_min_1_new_i(01),out_min_2_new_i(01),index_min_new_i(01), sign_value_new_i(01),sign_each_row_new_i(01),L_matrix_new_01);


^
 

Re: "signal or port name expected as actual in association element.(VSS-806)"

Please provide complete code such that I can help
 
Re: "signal or port name expected as actual in association element.(VSS-806)"

dftrtl said:
Please provide complete code such that I can help
Click to expand...

:)

With the exception of one word that is the exact sentence I did not even bother typing.

If you don't want help, please post vague questions like you did. If you do want help, post actual code to go with your error messages.
 
Re: "signal or port name expected as actual in association element.(VSS-806)"

Please don't use positional port mapping. The time you save writing the code will not compensate for the time you will lose when you debug it.
It can also be a good idea to have only one port per line.
I use emacs and I can "paste" an instance with all the port names predefined. This means that I don't spend any extra time with the named port mapping.
I guess that you can get similar help from other editors with a VHDL mode.

What is the type of the first port? You have connected it to "00" (without the citation marks) ? That seems strange.
 
Re: "signal or port name expected as actual in association element.(VSS-806)"

dftrtl said:
Please provide complete code such that I can help
Click to expand...
the code is big ,so I put the part of code that error occered
Code: 
type matrix1x96_big is array (1 to    4) of integer range -3000 to 3000; 
type matrix1x7sign             is array (1 to 0007) of integer range -1 to 1;
constant range_medium   : integer :=4095;
type matrix1x7_big             is array (1 to 0007) of integer range -3000 to 3000;
      
component total_1_a 
 port(sum                 : in    integer range 0 to 95;
      clk                 : in    std_logic;
      clr_in              : in    bit;
      L_matrix_row        : in    matrix1x96_big;
      length_row ,length_row_pre         : in    integer range 7 to 8;
      col_each_rowblock   : in    integer range 1 to 96;
      col_index_nonzero   : inout integer range 1 to 4;
      sign_value ,sign_value_pre         : in    matrix1x7sign;
      sign_each_row ,sign_each_row_pre      : in    integer range -1 to 1;
      index_min ,index_min_pre          : in    integer range 1 to 7;
      out_min_1,out_min_2,out_min_1_pre,out_min_2_pre : in    integer range 0 to range_medium;
      out_min_1_new       : inout   integer range 0 to range_medium;
      out_min_2_new       : inout   integer range 0 to range_medium;
      index_min_new       : inout   integer range 1 to 7;
      sign_value_new      : inout   matrix1x7sign;
      sign_each_row_new   : inout   integer range -1 to 1;
      L_matrix_new        : inout matrix1x7_big:=(0,0,0,0,0,0,0)
       );
end component;

total_01:total_1_a port map(00,clk_internal,clr_in,L_matrix_row,length_row_i,length_row_i_pre,col_each_rowblock_ii,col_index_nonzero_01,sign_value_i(01),sign_value_i_pre(01),sign_each_row_i(01),sign_each_row_i_pre(01),index_min_i(01),index_min_i_pre(01),out_min_1_i(01),out_min_2_i(01),out_min_1_i_pre(01),out_min_2_i_pre(01),out_min_1_new_i(01),out_min_2_new_i(01),index_min_new_i(01), sign_value_new_i(01),sign_each_row_new_i(01),L_matrix_new_01);
 

Re: "signal or port name expected as actual in association element.(VSS-806)"

An "inout" port can not be of type integer. In this case you should use "unsigned" or "signed" instead.

Are you planning to synthesize this and use it in an FPGA?
Try to avoid "inout" ports. Modern FPGA's don't have internal tristate signals, so if the synthesis tool can handle it, it is emulated.
If possible, help the tools by only using "inout" on ports connected directly to external pins.
I prefer to only use "inout" in the top entity and have separate "in", "out" and "enable" ports on the sub-blocks.
That is also the way to do it if you want to design a block for an ASIC, because you can probably not use "inout" even in the top entity.
No ASIC manufacturer want to have internal tristate signals.
 
Re: "signal or port name expected as actual in association element.(VSS-806)"

thank you,
( I analyzed the port total_1_a with out any problems about inout.)
I clear inout and use the standard port map.


the error is clear,
sum<=0;
tot:total_1_a port map(sum => sum,...)
but when I use elaborate ,I face with this error :
Code: 
Error: Connection to instance port sum is too wide 
	in routine a line 408 in file
 
Last edited:

Re: "signal or port name expected as actual in association element.(VSS-806)"

Please tell me how you plan to change direction on the integer inout ports.
With inout ports based on std_logic the driver in an entity is disabled by assigning 'Z',
and the port becomes an input.
 

Re: "signal or port name expected as actual in association element.(VSS-806)"

I saw code,I just put inout ,and the real I dont use signal as inout ,they just be out.

I solve the problem .
 
Last edited:

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