Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] Behavioral model or structural model ?

Status
Not open for further replies.
kmegamind

kmegamind

Junior Member level 1
Joined
Oct 2, 2012
Messages
18
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Location
Alexandria , Egypt.
Activity points
1,406
I am currently learning VHDL, And i understand the difference between behavioral and structural modeling, But i want to know which is better in synthesis (creates a more optimized code) ?, And on what basis should i select a certain model to work with ?
 

Behavioural Code : You write behavior of your circuit what you need in VHDL Language
Structural Code : You write code using logic gates but doing the same circuit behaviour what you need.

When you write structural code there is nothing for synthesis tool to do because you have already done it. It does not optimize any more.
Very Timing critical circuits you decide micro architecture by thinking structural code rather behavioral code.
 
To write the behavioural code the behaviour of the circuit u must know that also easy, when u know the structure of the circuit. compare to behavioural code structural code is quite comfortable for VHDL programming. for both the codings well known architecture is the important thing.
 

With behavioural code, you have to make sure you follow the correct templates to make sure it will synthesise - there is a lot of VHDL that will not synthesise. But using this style of code can mean more readable code, but does not garantee it. What is important is good documentation (good comments and association documents). But you are letting the synthesisor do more of the work for you.

This is a big strength of VHDL, there are a lot of things that are not synthesisable that allow you to create some very fast behavioural models for testing purposes. Things like wait statements, access types and protected types can be very useful in the right places.
 
If you are implementing large circuit at that time structural model is good, as in behavioural model, the complete behaiour of the circuit should be known.
 

Er.abdulrehman

In both cases we need full understanding. Your understanding is not correct.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top