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Verilog DFF questions

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shaiko

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I have some questions regarding the following verilog code:

Code: 
always @ ( posedge clk or negedge reset)
if (~reset) begin
  q <= 1'b0;
end  else begin
  q <= data;
end

First,
What is the difference between the ~ and ! operators ? Don't they both do the same thing ?

Second,
When do you have to use the "begin" keyword ?
 

~ performs bitwise negation whereas ! is a logical operator. In this case both will give u the same result.

Begin has to be used whenver there are multiple statements involved. For eg. if u had to assign values to multiple variables in the if statement u need to use begin. In this case u can skip begin and end. The result wont be affected.

Hope it helps...
 
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    shaiko

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1. Please give me an example when ~ will give a different result from !
2. You're saying that the DFF can be written like this :

Code: 
always @ ( posedge clk or negedge reset)
if (~reset) begin
  q <= 1'b0;
else
  q <= data;
end

?
 
Last edited:

1. ! 123 is 1'b0 whereas ~3'b101 is 3'b010.

2. Begin and end is for each if or else statement. Not for the if-else structure as a whole. If there are multiple statements under 'IF', use begin-end combination. If and else are to be treated as separate structures.

always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
else
q <= data;
end

This is not correct becoz begin should have a corresponding end for each of its associated if/else statement..

always @ ( posedge clk or negedge reset)
if (~reset)
q <= 1'b0;
else
q <= data;

Should work in this case since there is only one statement in both if and else.
 
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    shaiko

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That's very helpful.

I don't understand though why "reset" is under "negedge" in the sensitivity list...
The aynchronous reset of a DFF is level sensetive and not edge sensitive...As I see it, the code should be

always @ ( posedge clk or reset)
Click to expand...
and not
Code: 
always @ ( posedge clk or negedge reset)
Would you agree ?

- - - Updated - - -

That's very helpful.

I don't understand though why "reset" is under "negedge" in the sensitivity list...
The aynchronous reset of a DFF is level sensetive and not edge sensitive...As I see it, the code should be

Code: 
always @ ( posedge clk or reset)
and not
Code: 
always @ ( posedge clk or negedge reset)
Would you agree ?
 

Tht purely depends on ur application... If the reset is edge triggered use negedge/posedge, else just reset/!reset...Normally for asynchronous resets, just reset is enough....
 

rvidya,

I've never heard about edge triggered resets.
An asynchronous reset is always level triggered...
 

rvidya,

Can we say that the "begin" statement is for "beginning the assignment"?
 

No. "begin" is for beginning a more generic block of code that has a nice name that I forgot from the formal definitions.... block declaration, that was it. So begin is the beginning of a block declaration. And you can stuff more things inside a block than just assignments.

Random terms you can google: "verilog bnf begin block declaration".
 
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    shaiko

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shaiko said:
I don't understand though why "reset" is under "negedge" in the sensitivity list...
The aynchronous reset of a DFF is level sensetive and not edge sensitive...As I see it, the code should be

Code: 
always @ ( posedge clk or reset)
and not
Code: 
always @ ( posedge clk or negedge reset)
Would you agree ?
Click to expand...

from formal point of view, the first notation [ (posedge clk or reset) ]
would trigger reset action whenever reset signal changed its level;

the statement:
always @(posedge clk negedge reset)
if ( !reset ) X <= 'b0;

triggers reset action when reset goes LOW and keeps resetting
as long as 'reset' IS low;

j.a
 

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