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Macro dominated design+suggestion for floorplanning

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raghuvlsi

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Hi,

My design consist of 166 macros and 650k instances(40nm,TSMC, 6 metal layers). Macros vs logic occupied area ratio is 85%:15%

std cell area:807358.653um2
macro area : 4580736.839um2
We don't have spec for the block area.I need to start with cell density with 60%. And we have to decide area based on the design complexity.
Can any one suggest how much core utilization have to maintain with 60% cell density?
How much Width and Height?
I am using cadence tool.

Thanks,
Raghu
 

What is the target utilization after routing? Try to import the design in SOC-Encounter/EDI. Then you change the core-area of the design as per your needs.

My suggestion is, you can start with 75% Utilization as the design is Macro intensive & there won't be much growth in area.
 

kumar_eee said:
What is the target utilization after routing? Try to import the design in SOC-Encounter/EDI. Then you change the core-area of the design as per your needs.

My suggestion is, you can start with 75% Utilization as the design is Macro intensive & there won't be much growth in area.
Click to expand...

Hi kumar,

Thanks for reply.
Now placement optimization(preCTS) run is going on. I have observed the log file, its look as more H and V congestion.
Can you suggest macro overhead area and standard cell overhead area , and also core area based on my design?

Suggested by you, shall i take core utilization is 75%? Then cell density is showing 35%.
My lead suggested me the design need to start with 60% cell density. Is it suggestible?
 

Look at the place where more congestion is reported.

Is it in between the Macros? If so, look at why it is happening? Are there any std cells sitting in that macro area other than inverters & buffers? Or may be your macro has more pins. You may have to spread the Macros to avoid the congestion.

Start your design with cell density of 70%. Whats the core when you keep 60% of cell density?
 
Hi Kumar,

Thanks for reply.

No congestion between the macros.

In design i have seen lot of congestion in standard cell logic area. Especially in cpu1 and cpu2 modules. Each module consist of 260 k instances.
In module, lot of detoure connections. Cell density is almost 70 to 80 % range. I dont know why it is taking detoures.

Can you tell what is the reason for congestion (5%(H),10%(V))?

Thanks ,

Raghu
 

Good that you don't have any congestion between macros.

Have you given enough area for the CPU1 & CPU2 respectively?
Are there any macros which belongs to CPU1 & CPU2 modules? If so, you may consider provinding some area between these modules.

Analyze the design why its detouring the routing. What kind of cells placed in that area ( like OAI, Complex cells.. etc)?

At which stage you're in right now?
 

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