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[Moved] Verilog Question about instantiating

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geozog86

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First of all i want you to forgive me for placing this Q here, where should I? didn't find any match for verilog/vhdl questions!

And now the question, which is pretty basic: when i instantiate a module in another module, and i open a parenthesis to give values to the inputs/outputs, i have

inst a (.in1(value1)
.in2(value2)
.out1(value3)
);

What exactly happens with the .commands? Are the first 2 (in1/2 take the values1/2) but for the output (out1 write your value in value3)? Or what? Am i giving value to the output???

Sorry have no experience in verilog, only vhdl, and i can't find anywhere the answer to my question!

thx
 

Re: Verilog Question about instantiating

the dot is used to Tie the variables mostly ina different module or loop. Example the varialble "var_in_this_module" is tied to the variable (a kind of assign) in the other module or instance by ".var_in_other_module(var_in_this_module)" .. as soon as var_in_this_module gets a value its transferred to var_in_other_module... hope u get me...
 
Re: Verilog Question about instantiating

Thx for the reply, i re-read the code this morning, but my question remains: How can i tie the output of the "other module" to any value of this module?? Shouldn't i only tie the inputs of the other module, and USE the output the other module produces? Maybe it works the other way then, and when var_in_other_module_OUTPUT_changes then it is transferred to the .var_in_this_module?
 

Re: Verilog Question about instantiating

mod1 mod1_tb(.en(tb_en),.rst(tb_rst),.clk(tb_clk),.count(tb_count));

in d above example, mod1 is my actual module ... mod1_tb is another module .....
.
the variables .en,.rst,.clk are from module 1..
.
the variables tb_*** belong to mod1_tb...
.
this is how u tie them.. ensure that they r in d same project/workspace....

---------- Post added at 10:55 ---------- Previous post was at 10:53 ----------

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// this a sample program to help u learn how to tie the variables
// hope if u understand the module u ll realise...
/// also try simulating them
 
module mod1 (en, clk, count,rst);
input en,rst;
input clk;
output reg [3:0] count ;
 
always@(posedge clk) 
begin
      if (en==1'b0) begin
         count<=4'b0000;
      end else if (en ==1'b1) begin
         count<=count+4'b0001;
    end else if (rst) begin
         count<=4'b0000;
    end      
        
end
endmodule
 
module mod1_tb ();
    reg tb_en, tb_clk, tb_rst;
    wire [3:0] tb_count;
    
mod1 mod1_tb(.en(tb_en),.rst(tb_rst),.clk(tb_clk),.count(tb_count));
 
initial
begin
 
tb_en=0;
tb_rst=0;
tb_clk=0;
 
#50 tb_rst=1;
#50 tb_rst=0;
#50 tb_en=1;
#1800 tb_en=0;
   
#2000 $finish;
end
 
always
begin
#50 tb_clk=~tb_clk;
end
endmodule
 
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