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Before CTS, The clock will be ideal, and will not have SKEW info.
After CTS, the actual clock is propagated with latency and skew info. Set the clock in propagated mode and report the timing. Check the report for the clock propagated in the report.
I'm sorry if this discussion is not related to Physical Design.
during the synthesis or with a STA tool, there are some command like check_constraints, with analyze that all flops are clock with a clock properly define by create_clock or something else.
during the synthesis or with a STA tool, there are some command like check_constraints, with analyze that all flops are clock with a clock properly define by create_clock or something else.
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