Logic element vs Macrocell

How does an FPGA logic element compare to a macrocell ?

A better question: how does a logic element in component ABC compare to a macrocell in component XYZ, for a given design?

From what I know, there's no easy & hard rules. For one, because a design 'maps' in different ways onto the architecture of different device families, and this may also depend on what optimizations are done. So it may fit very well in device ABC, but rather inefficient in device XYZ (even if those are considered roughly equally big). For another design it may be the opposite.

One way to tell is select a device of your choice in the design software, and go through the actual implementation steps. That would either fail (and say so why), or succeed & thus let you know how much of the chosen device's resources are used. Change optimizations / settings as desired, repeat & compare with result for other device(s).