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[SOLVED] LDO pass transistor design

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sri.sagar

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Hi everyone,
I am designing capless LDO and i have connected the gate with some control voltage and source to 3.3 VDD/vin and at the drain i have 2.8v (resistor network) along with my load current 0f 50mA, i do not know how to fix the W/L for this pass transistor and what parameters to be measured to calculate the W/L for it . can anybody please tell how to fix the size of the pass transistor of LDO.

Thank you.
 

Dear sri.sagar
Hi
I think it is a bit hard , to guide you without your schematic .
Regards
Goldsmith
 

pass_transistor.png

here is my setup, can you please guide me.
 

Pass transistor length is the minimum available (unless you find leakage issues in disabled mode) and the width is the minimum required to carry the specified max current while keeping itself in saturation at the specified drop-out across all corners. Well that is stating the obvious. But this is usually not a difficult design decision, do you have any specific problems?
 
Hi,
Step 1, find out or define the min OCM(output common) voltage;
Step 2, apply this min OCM to the gate in your attached SCH;
Step 3, SIM it with width swept at max load, and ss corner, and hot temp;
Step 4, find the width that VDD - VOUT < specified dropout in the SIM result.
 
thank you so much for all, i followed leehying and chechmate steps, i fixed the size of pass transistor, thanks once again.
 

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