conv_integer equivalent in verilog?

I want to a compare a variable of type 'genvar' (index used in generate-for loop of verilog) with a 3 bit vector.

Let 'i' is a index variable in generate*statement in both VHDL and Verilog.

In VHDL, this will do

if (i = conv_integer(A(2 DOWNTO 0)) THEN
B <= C;
ENDIF;


What is the equivalent of the above code in Verilog?

Will this work?

if (i == A[2:0])
B <= C;

Pl. help

Will this work?

if (i == A[2:0])
B <= C;

Click to expand...

Yes. Verilog doesn't use strict types, so you can easily compare integer to bit vectors, that are understood as unsigned integer by default.

u can compare like that but it is a bad practice better to write code for comparator.

@FvM and @nisshith

Yes. I realized that by writing and testing some sample code by writing in the above way.

Verilog module

module conv_int (b,a);

input [2:0] a;

output reg b;

integer i = 2;

always @(*)
begin
if( i == a[1:0])
b <= 0;
else
b <= 1;

end

endmodule



VHDL module (equivalent)

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity conv_int is
port(a : in std_logic_vector(2 DOWNTO 0);
b: out std_logic);
end conv_int;

architecture beh of conv_int is
signal i : integer := 2;

begin
process (a,i)
begin
if ( i = conv_integer(a(1 DOWNTO 0))) THEN
b <= '0';

else
b <= '1';

END IF;

end process;
end beh;

The RTL views are in the images 1 and 2 respectively.





Per Verilog design RTL view, comparison is 32-bit. 32-bit integer and 30-bit vector(although it is declared as 3 bit)

Per VHDL deisignRTL view, comparison is 2-bit, which is optimized.

How can this be more optimized in Verilog?

in verilog if u write

if (i[2:0]==a[2:0])

I think it will create a 2 bit comparator.

How can this be more optimized in Verilog?

---------- Post added at 17:53 ---------- Previous post was at 17:52 ----------

How can this be more optimized in Verilog?

Click to expand...

RTL view is more or less meaningless to determine synthesis efficiency. I would be surprized if you see superfluous bits in the gate level netlist.

P.S.: I see a problem, that the shown code snippets synthesize to "nothing". You need in fact to define a reasonable test design where the involved variables aren't constant.