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capless LDO line regulation problem

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sri.sagar

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Hi everyone, I am a newbie to the analog field and I have implemanted robert millikens capless LDO in 90nm technology,which has 3.3V input and 2.8V output for a load of 100pf(internal) with max load current of 50mA. I am getting line regulation of 31mV/V at 50mA(max) and 11mV/V at 0mA(min) and psrr is -35dB at 100Khz, accourding to my knowledge it is bad. how can i improve my line regulation and psrr. and all other parameters are turning out to be good ,say my open loop gain is 61.2dB ,load regulation is 0.33 V/A,settling time is 2us.

Please help me.
thanks
 

As the dominant pole is at the gate of the pass transistor, supply rejection would suffer after the first pole. The Milliken architecture by design does not do anything to improve it. I suppose that your dominant pole is in the range of 3KHz, if so this is what you can expect in the best case from the design directly.
 
With 500mV of headroom, your pass FET is a resistor more or
less and only the loop amp gives you any PSRR.

Now within the loop amp are many opportunities to couple
and amplify supply-difference noise. Especially current mirrors
in bias racks tend to magnify supply voltage noise into bias
current noise. Cascoding is good for DC noise but needs very
stiff gate to stand off HF AC. Pulling through a common-gate
FET can buck a lot of AC.

An oversized FET will give you trouble keeping the gate moving
at high frequency; too small a FET requires excess gate drive
and puts the device even more linear / resistive. Is the pass
device "right sized", and then the amplifier drive sized to that?
 
Hi, thank you so much for the reply
@saro_k_82: yes the dominant pole is at 3KHz
@dick_freebird: I increased the size of the pass transistor and now my line regulation is around 20mV/V is there any other way to decrease it further ,but my open loop gain decreased to 56.292 dB,
 

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