Need interview questions on Advanced Floorplanning techniques ?

Hi,

I need to know what kind of advanced floorplan techniques we use for doing the floorplan other than checking the flylines ? How are the memory macros placed and are their any specific rules we have to follow while placing these ?

Please explain in detail.


Thanks
Pavan

what is the guarentee that the same questions will be asked????

trust your knowledge and yourself , then go and face... see what happens......... no body has a predefined questions .. everyone ask random questions what comes to their mind at that time... all these interview questions are not real...

if you have a book or site published for it, then the interviewers will never ask those questions.... at least i dont refer any site or book before asking questions....

ckshivaram said:

what is the guarentee that the same questions will be asked????

trust your knowledge and yourself , then go and face... see what happens......... no body has a predefined questions .. everyone ask random questions what comes to their mind at that time... all these interview questions are not real...

if you have a book or site published for it, then the interviewers will never ask those questions.... at least i dont refer any site or book before asking questions....

Click to expand...

Ok then let me ask specific questions in floorplan.

1. If we have many memory macros how do we stack then together?
2. What will be the starting utilization and aspect ratio if we dont have this info from the top level?
3. On what basis is the power planning done? i mean the inputs ?
4. Why is static IR analysis done in the floorplanning stage as we are not analysing the dynamic power? Do we require std cells and macros for static IR placed while doing IR analysis ?
5. What is the criteria for the good marco placement in the floorplan?

Please provide info in detail.

Thanks

Hi Pavan,
1. Macros are aligned such that the pins, pin orientation, channel between memories, any extra spacing to be left around, their power source are taken care. Overall the macro placements have to give close to rectangular space for the standard cells. Secondary issues have to be taken care with placement and routing blockages and utilization nos.
2. Starting utilization depends on the technology, to start off ppl take a safer stand with 55%
3. Analysis is done based on the cellcount and the average and peak consumption based on that the power strap ratio is determined.
4. Based on the activity factor, one would know wat would be the minimum I requirement, to ensure that the power routes are serving the I requirements, static IR is done at FP or place stage.
5. Found this in another post:
Tips for macro Placement

1. Place macros around chip periphery.
If you don’t have reasonable rationale to place the macro inside the core area, then place macros around the chip periphery. Placing a macro inside the core can invite serious consequence during routing due to a lot of detour routing, because macros are equal to a large obstacle for routing. Another advantage to placing the hard macros around the core periphery is it's easier to supply power to them, and reduces the change of IR drop problems to macros consuming high amounts of power.
2. Consider connections to fixed cells when placing macros.
When you decide macro position, you have to pay attention to connections to fixed elements such as I/O and perplaced macros. Place macros near their associate fixed element. Check connections by displaying flight lines in the GUI.
3. Orient macros to minimize distance between pins.
When you decide the orientation of macros, you also have to take account of pins positions and their connections.
4. Reserve enough room around macros.
For regular net routing and power grid, you have to reserve enough routing space around macros. In this case estimating routing resources with precision is very important. Use the congestion map from trialRoute to identify hot spots between macros and adjust their placement as needed.
5. Reduce open fields as much as possible.
Except for reserved routing resources, remove dead space to increase the area for random logic. Choosing different aspect ratio (if that option is available) can eliminate open fields.
6. Reserve space for power grid.
The number of power routes required can change based on power consumption. You have to estimate the power consumption and reserve enough room for the power grid. If you underestimate the space required for power routing, you can encounter routing problems.

Hope this helps..

Have a look on this thread:
https://www.edaboard.com/threads/234001/#3