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Hi all,
I was trying to understand if and how it would be possible to query a FSDB file dumped after a simulation and without any other knowledge
about the design that it "describes", get the name of the fastest signal in it and its frequency. Is that possible either by use of some command,
or...
Hello,
a very generic synthesis script is used in our project that loads all available std cell libraries and memory modules
libraries beforehand. After synthesis the design has of course utilized only a couple of them and a couple of different memories.
How can I find out exactly which...
Yes this is what I'm doing, please read previous posts. Before enabling power-driven clock gating I simulate and fetch SAIF annotation of the netlist to be clock gated. Therefore the tool knows which registers are busy and which arent't.
The thing is that it decides to go only for 60% of the...
Please I would like to have some opinions!
I think that the power driven algorithm doesnt take into account the muxes that ar gonna left behind if it decides not to clock gate some registers. So in the end that's why I get more area and more dynamic power.
Is it that the algorithm is not...
Yes, the flow I'm following is as follows:
After elaboration (GTECH) I insert clock gating and compile once. No saif annotation here.
Then after i get the first clock gated netlist, I simulate it and get a saif file out of the simulator. Then I go back to the synthesis flow, enable power...
insert clock gating
Yes!
That's a very good explanation! I was just checking powercompiler manuals now and was thinking that this could be the reason after seeing some nice pictures it has in there.
Now I have another question which bothers me.
When I do power driven clock gating with saif...
why clock gating using muxes
Hello all!
I'd like to ask you if you have noticed the same as I did when inserting clock gating in a design. I use Synopsys tools, i.e. Design Compiler-PowerCompiler for that.
So, what I observed is that when I apply clock gating the circuit area shrinks!
A...
power calculation cell
thanx for your reply!
I have this ebook and started reading it but got dissapointed with the way it is written. Moreover some things it provides are outdated, so i quit...
Instead I started reading synopsys manuals to get a good idea of the tools and I think that was a...
advanced_asic_chip_synthesis_-_bhatnagar.pdf
Hello!
I was looking the other day at a .lib file for some libraries used, trying to find out how power is calculated by power estimatiob tools out of the library data provided
for each cell.
So, for each cell the library provides the following...
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