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PICKit2 Owners
I think can forget about it.
My Aim for making PICkit is to program the chip for UBW32. But I just realised the PIC for UBW32 doesnt come in DIP package, so even if I get it, I cant possibly DIY the UBW32 board on breadboard =__=
xst:2677
argh... I'm getting alot of the following error when i tried to do synthesis
:Xst:2677 - Node <myRAM/Mram_mem1> of sequential type is unconnected in block <encoder>.
I got this error from myRam and many others... some kind people please helpme..
xxx is myRAM/Mram_mem1-128 of my...
does anyone kno what is this error? I'm getting alot of it from Modelsim, despite that Im able to compile w/o syntax error on the webpack.
I'm using verilog code for my proj...
# ** Error: (vsim-23) Unable to change to directory path "secureip".
# No such file or directory. (errno = ENOENT)
Re: State Machines
my count is actually a internal signal instead of a input signal. so what happens is this count is incrementing by itself when those inputs are being held high.
I see this in the hardware, but not in the software.
i've no clock, no changes made to nextstate, and so no...
Re: State Machines
something like a asynchronous reset that resets my count to 0 and state to state1?
in this example, i never intend to use the 1st process. just merely want to see how the 2nd process works out when in1/in2/in3 has something. but it happens that it keeps on retriggering...
State Machines
signal output: std_logic_vector(3 downto 0);
signal LED : std_logic_vector;
signal count : integer:=0;
process(clk)
begin
if(clk'event = true and clk='1') then
state <= nextState;
end if;
end process;
process(state,rst,in1,in2,in3)
begin
LED <= '0';
case...
Re: Block Rams
I had the clock on for a few clocks
but every clock the datain changes....so i actually wrote in diff data
and my output came out as expected.
the full flag reset...what does it does?
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