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Recent content by zcg

  1. Z

    error in vhdl code,please check it?

    "if clock'event and clock='1'and reset='0'then " what's this? what kind of circuit do you expect it will be synthesized?
  2. Z

    which is better to use : Registers or RAM ?

    Excuse me, I don't think you have clear idea of RAM & REGISTER. Added after 5 minutes: What are you confusing for? For 2K store, just go to use RAM. According current process, 2K RAM(1T or 6T) is doutbless more efficient then reg.
  3. Z

    SystemC , Systemverilog , vera , specman...

    First ,specman E is good but not generally supported by other EDA company. System C and system verilog maybe have more bright future to be common standard. Second, I think you have a wrong idea of verification job. In fact a good verification engineer should have more knowledge than RTL...
  4. Z

    What is better for UWB field, CDMA or OFDM?

    cdma vs ofdm funny~~~hoho why not study some basic communication books firstly.
  5. Z

    Where can I get the "HDL Chip Design" book by Smith?

    HDL Chip Design book hehe, I don't think he wanna cost money on it.
  6. Z

    Floating point to Fixed point conversion

    float to fixed point conversion in q formats used to :mathcad(floating) -> C(fixed)->RTL now: simulink -> RTL
  7. Z

    CORDIC DST implementation

    a good paper about CORDIC
  8. Z

    Some good paper in Chinese on PLL design

    how to read it? Pls give the reader link.
  9. Z

    Where to get QPSK Modulator with I/O = 1Mbps/100Mhz RF?

    QPSK Modulator I am interest in the design methods of that(implemented with FPGA). Does anyone recommend some relative paper?
  10. Z

    Can anyone share some materials about digital PLL?

    Who can share some implementation methods of DLL? Thanks a lot.
  11. Z

    Opinions on performance of Virtex-4 FPGA

    Virtex-4 I have already got the samples of V-4 for our dsp project. It is said that V-4 is the lowest cost FPGA.
  12. Z

    constrains in the sythesis

    It would be better if someone can upload a script sample. Thanks a lot if anyone can give me a constrains script of synpilify pro.
  13. Z

    about TSI(Time slot interchanger) design?

    nobody answer me? I just want to know how to design input/output buffer. As you known,each channel can be set on different data rate( 2.048Mb/s,4.096Mb/s.....) and the rate of input channel may be not macth with that tranmit channel. So there will be many individual fifos for data store...
  14. Z

    about TSI(Time slot interchanger) design?

    Where can I get some hardware design guide ? Can any kind people do me a favor? I am really a new man in TSI field.
  15. Z

    CIC decimation function: integrator, downsample, comb filter

    Re: CIC decimation you wrong . cic comb filter is IIR(one tap) not FIR Can someone tell me the relationship of CIC decimation and GAIN? Which part efect the final GAIN? (integrator or decimation or IIR?)
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