Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi volker@muehlhaus and BigBoss
You help me much.
Do you mean the GND at bottom of substrate by saying " mutual inductance effect between the inductor and the ground frame"?
I see you are using Sonnet, but what do you think of using lumped port in HFSS to de-embed following attaching picture ?
I very appreciate your reply.
The M1 ring is not closed but cut in one terminal. Do you think what the M1 ring is for?
perfect E boundary in bottom of Sub is used for ground in spiralinductor.pdf, I do the same to verify PDK inductor.
And connect spiral ring with ground ( bottom of Sub )...
Hi friend, I'm facing the same problem when simulating inductor from PDK in TSMC. The Q factor is low unless changing guarding material from M1 to pec. It seems that the guard ring is not current return path. what do you think of if?
Do you deal with it?
Thanks
I export gdsII of inductor from virtuoso. the guard ring is M1 of tsmcN65 1p9m process. I think the guarding ring may be used as current return path in this way it connects two ports. As you know there are always guard ring in PDK like tsmc. I using two port s-parameter, calculate L...
I'm simulating a m9 spiral inductor with m1 ground ring in HFSS.
The L is close with data of PDK, but Q factor is very low compared with PDk.
I think the narrow is reason why Q factor is low, but as you see, ground ring indeed is narrow.
I think ground ring as current return path should not be...
The launching code as follow
system('E:\Synopsys\Hspice_F-2011.09\BIN\hspice techchar.sp > techchar.out');
After simulating, techchar.out is not created.
I don't know why.
**************************************************************************************************************
original...
Hi erikl, thank you a lot. Does the book talk about the voltage biasing like cascode ckt and how to deal with ICMR and output swing ?
It seems a little different with EE214 handout of Murmman(design based on gm/id)
If SR, DC gain, f(-3dB), load capacitance
It seems like that there is not clear direct relation between gm/Id vs. gmro since ro is just a part of gmro when gm is not determined
in differential input amplifier with current mirror load. the DC gain is gm1*(ro1|ro2), but I think it's not easy to...
how to determine Gm/Id and how to bridge it with gain
In analog IC design, I extract some parameters through simulation but not accurate,sometimes 50% error.
I feel Gm/Id method may be a better choice. but how to determine IC i should used in design.
however I don't know how to relate IC with...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
