Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by you23

  1. Y

    distortion (INL) problem in sigma delta modulator

    Hi, I designed 2nd order sigma-delta modulator (1bit), and made chip, and measuring now. I use FPGA after modulator output. the FPGA is used for sinc3 decimation filter (16bit out). I have a distortion problem for measurement. test condition; VDD=3V, VSS=0V, VREF+=3V, VREF-=0V...
  2. Y

    INL & Gain of sigma-delta modulator

    I am testng sigma-delta modulator (SC) that I designed. *2nd order - 1bit output(SC) *fully-differential input *fclk=500k *gain=1 *VDD=3V, Vcommon=1.5V in these case , 1) Vinp=Vcommon, Vinm=0to3V swep ---> gain=almost 0, INL=4LSB 2) Vinm=0to3V, Vinm=Vcommon swep ---> gain=lower than 0...
  3. Y

    Fully Differential Opamp Verilog-A Model

    Hi I found cadance example. And, tried to modify this example to add output limitation. But. I could not. Pls tell me. Thanks.
See more

Part and Inventory Search

Back
Top