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pll simulations in cadence
It is very diffucult to simulate the PLL in cadence system expecially for the case of high N value.
Instead, you can use verilog-A to model the VCO with its phase noise and to model other components. Then simulate PLL, it will be good.
But you need to make sure...
Re: Test problem of DAC
Could you measure the output by hand using a scope ?
If you can do it, you will find the problem.
If the measurement data by yourself is a stable value from time to time,
there will be accuracy problem in your ATE.
If the measurement data is also unstable, you may...
If your circuits are all 3V devices, there will be no scaling effects from 0.18um process to 0.13um process.
If your circuits are all 1.8V device, there will be some scaling effects from 0.18um process to 0.13um process.
Usually, there will be about 40~50% shrink for all digital circuit.
For...
Re: VCO design
For such low frequency operation, I usually use the RC relaxation type oscillator.
It can provide good phase noise and low power consumption.
By the way, you may add a hysteresis circuit to prevent the glitch issue in such low frequency operation.
Re: DAC characterization
DAC dynamic simulations include
1. setting time simulation:
input from 0000 to 1111 (4 bits example).
find the time to settle output within 1/2LSB
2. Glitch simulation:
input from 0111 to 1111
find the glitch energy in the output waveform
3. THD...
In my experience, ring oscillator will be varied by a big amout.
For example, typical is 300MHz in a specified controlled volatge.
After mass proudction, we can measure as low as 150MHz and as high as 450MHz.
Therefore, you need to cover process variation in your VCO design.
For your reference.
1. monte carlo simulation is used to simulate the mismatch effect to the circuits.
Usually, the width, VT, R, and C are varied to see what happen to your circuits.
2. corner simulation means process variation simulation. It's part of PVT.
3. PVT simulation: P stands for process, V stands...
pros of thermometer code:
1. no glitch will be happened compared to binary code
2. easy understand
3. Often used in current DAC and R-ladder DAC
cons of thermometer code:
1. bit number is large. (8 selections need 8 bits)
2. need decorder if input is an binary array.
The bigger ratio of BJT means it can tolerance more offset voltages in the BG circuits. Usually I use 1:8 to save power and area. But the variation in mass production is a little big but can be accepted.
First, you make sure that your device models include ESD model ?
Becasuse commerical models like TSMC dont's provide ESD models in their device. It is diffucult to simulate the ESD performance in design phase.
what is an engineer mts
Technical staffs often has some kinds of good skills in some areas. Like ADC or others. In analog IC design house, they takes the job of diffucult IPs or circuits in a project especially when the project is new for this company. In others words, they build prototype...
Re: what is monte carlo ? if any one know accurately plz tel
Monte Carlo simulation is try to simulate the impact on different circuit;s parameters.
It varis one or more paramter randomly in the same time to get different results. Therefore, you can see the impact on your circuits from those...
Re: cmos comparator
CMOS comparators usually compose of a preamplifier and a post-amplifier. The preamplifier is a linear gain amplifier and the postamplifier is a latch-based amplifier.
When the input change is larger than the input range of the preamplifier, the comparator enters the...
Folded-cascode OPs are suitable for any kinds of application including SC
I think you need to consider the stability issue in your SC application.
Please simulate the phase margin and gain margin for your application.
You also need to simulate the phase margin for CMFB loop.
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