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Recent content by yesme@

  1. Y

    Synchronous and Asynchronous Design

    Asynchronous circuit may consume less power than synchronous circuit. But it's not true for all cases.
  2. Y

    what is hot-topic in digital design now?

    Reconfigurable SoCs Reusable design methodologies Low-power techniques Design-for-Test/Testability Fault tolerance
  3. Y

    Comparison of Perl and Tcl script languages

    perl vs. tcl For EDA, tcl is prefered !
  4. Y

    How to implement DFT with single scan clock

    Use a dedicated clock for test process. This can be done by a mux
  5. Y

    What is the exact design flow of any digital chip?

    Re: Digital Design Flow Design flow: Behavioral Description-> Behavioral Synthesis-> RTL Description-> Logic Synthesis-> Gate Description-> Technology Mapping-> Technology Network-> Layout-> Mask Data-> Manufacturing-> Product-> Testing-> Good Product
  6. Y

    Problem with nc_elaborate

    Hi guy, I done a co-sim SystemC/Verilog netlist. It was ok when I tried a single unit. When I tried an other co-sim with 15 units, it did not work. There is a problem with cadence tool (nc_elab). I don't know why ? It seems that the co-sim is too big. Anyone know what happen !!!!??? Tks,
  7. Y

    How to estimate the soc chip power consumption?

    U can use Prime Power to estimate power consumption.
  8. Y

    What are the various tools available for LAYOUT ?

    Orcad & Circuitmaker are used for System-on-Board design, not GDS. For LAYOUT, you should use Cadence, Synopsys, etc.
  9. Y

    want vhdl to verilog convertor for windows or linux

    You should use Design Compiler (DC) of SYNOPSYS. Write a script and use tcl-mode of DC.
  10. Y

    Problem with co-simulation

    OP_DATA_ack is an input port of node_gate.h module and it is declared as follow: sc_in < sc_logic > OP_DATA_ack; In the Verilog HDL file, from which we get the netlist, the OP_DATA_ack is a std_logic input.
  11. Y

    Problem with co-simulation

    I have got an error message when doing a co-simulation (SystemC & Verilog HDL (netlist)): # ** Fatal: (vsim-3681) No type information available for SystemC primitive channel 'signal_84' connected to HDL signal '.testbench.test_wrapper.node_gate_i.OP_DATA_ack'. # Each SystemC channel/port...
  12. Y

    question about fault coverage?

    I think that the fault coverage of 96%+ is accepted in large design. We have to trade off between fault coverage with test time, overhead of test structure, cost of ATE, etc. Added after 1 minutes: U should take a look at many proposed works in DFT domain
  13. Y

    Need advices for buying an FPGA evaluation kit

    money doesn't exceed 500$ for both of HW and SW - it's ok ? I prefere Xilinx.
  14. Y

    Need advices for buying an FPGA evaluation kit

    Hi guys, I want to buy an FPGA evaluation kit for studying. I have a little of money, so which kit I should buy ? Thanks,
  15. Y

    Scan test theory for ATE

    scan test theory What do you mean: use ate for scan test or ate testing ?
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