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Recent content by yeewang

  1. Y

    How to convert and connect sc_clock to sc_in<sc_logic>

    systemc question sorry, i just typed in an example, the sc_clock constructor is NOT complete.... in the real code, I did use the code piece like you wrote. that's not what my question is about.
  2. Y

    How to convert and connect sc_clock to sc_in<sc_logic>

    systemc question what 's the easiest way to convert and connect sc_clock to sc_in<sc_logic> port. eg. sc_clock clk; .... .... inst *a; a = new inst("instance"); a->clk( ***** ); // in a, clk is declared as sc_in<sc_logic> I need to connect sc_clock to this a->clk but due to the...
  3. Y

    how to use "compile" when have same design

    current_design D_SUB compile set_dont_touch ..... current_design TOP compile .... sth. like that.
  4. Y

    what is tool to model memory

    denali is a company it has a product memory modeler (pureview). you can check their website.
  5. Y

    Problem with CLK in DCM: the signal is not getting locked

    CLK in DCM see if your input clock frequency sits the acceptable range of DCM.
  6. Y

    Is system verilog the future??

    i agree with nandy. i personally think systemC will have a brighter future for it has free simulation and a bunch of guys working on it in OSCI, it can be easily adopted by software engineers, it has good link between different abstraction levels and etc. BTW, nandy, I tried your tool a little...
  7. Y

    Does Thold affect clock period at all ?

    . _____ ____ -----|D Q|-----comb logic----|D Q|---- -----|C | ---|C | | |____| | |_ __| |---------------delay buf--- | try caculate the timing for this simplest circuit. Just given Tsetup, Thold...
  8. Y

    Does Thold affect clock period at all ?

    yes, Thold doesn't affect clock period normally. but sometimes it affects the slowest frequency you can run.
  9. Y

    Looking for scrambler algorithm for wireless system

    scrambler typically, the scrambler is a LFSR, just as what people use to generate pseudo-random numbers. for a specific startand, like 802.11g, you should read the spec.
  10. Y

    What is timeborrowing related to Static timing anaylsis?

    timing borrow timing borrow, we refer to use latch to borrow time, which is typically half a cycle. retiming, is to move register forward or backward through the combinatorial logic to balance the timing paths on every stage in the nearby register chain.
  11. Y

    Cypress EZ-USB FX2 streaming problems with CyAPI and CyUSB

    cyapi to fully use the bandwidth of cypress FX2, which is a USB2.0 device, the PC has a tremendous workload. As we observed on previous projects, during the streaming process, any window-dragging will cause temporary packet stall. It's sorta system limit. Not caused by driver or sth.
  12. Y

    What is block RAM and how to use it in Xilinx devices?

    what is block RAM? go check the application notes from Xilinx, they're better than anyone's explanation. just some hints, the easiest way is use coregen to generate block ram clusters and simulation models.
  13. Y

    advantages of C over C++,PERL?

    C is of the best run-time effiency among almost all languages
  14. Y

    [Help]Verilog Problem?

    guy, it's easy. do like this. reg [127:0] temp; temp = chip.mem[i]; data={temp[127:63],temp[127:63]} ; have a try.
  15. Y

    Chipscope is not working correctly

    Re: chipscope problem almost.
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