Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hello all,
I am expecting my clock to jitter by -5% or +5% in real life, and I have to take that in consideration while writing my RTL, because many values and cases depend on the period of my clock.
My question is: is there a common way to detect or account for clock jitter in RTL ? it...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.