Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Yarrow

  1. Y

    Standard cell design and design rules

    Thank you for the reply. Typically, I used "DFM"-like approach in the past. However, since I am optimizing for area this time around. I guess I will use minimum rules, but avoid them whenever I can. Hopefully since this is a prototype run it wont have a significant impact.
  2. Y

    Standard cell design and design rules

    Hi, I am designing some standard cells in 65 nm and I was wondering if it is normal to design standard cells using minimum design rules or DFM rules? My thought is that one would like to make the standard cells as compact as possible, but to do this one violates the recommended design rules...
  3. Y

    [SOLVED] Capacitor layout in DACs

    Got it, thanks erikl!
  4. Y

    [SOLVED] Capacitor layout in DACs

    Hi, I am designing a charge scaling DAC. I was wondering what distance should be used between the capacitors in a capacitor array DAC? I imagine that using minimum distance between (poly-poly) capacitors is not ideal due to increase in the parasitic capacitance via the fringing capacitance...
  5. Y

    Power and Delay calculation in Cadence Schematic Editor

    There is also a pwr output available if you go to ADE → Outputs and save all power computations. Then it is also easier to find out which •t your sub-blocks are consuming most /least power. You may also want to check out specremdl if you are doing more advanced/automated characterization.
  6. Y

    Bulk contacts on the Standard cells

    To my knowledge LVS i tricky when using standard cells from fab ( I take it you only see the abstract view and not the full layout?) If so you need to use a black box approach where you treat the std cells as black boxes with IO. When it comes to the physical bulk contacts, in a place and route...
  7. Y

    About Standard Cell Libraries

    Just a followup question which has interested me in a long time. Can anyone confirm if the .lib files from foundries are based on simulations or measurements ?
  8. Y

    LVS using standard cells

    Hi all. I am trying to do LVS using std. cells from foundry. I am using Cadence tools with Calibre LVS. I am currently using an inverter (with input and output pins) as a test case. 1. Anyone know how to handle inherited gnd/vdd in layout? I see them in the schematic netlist, but I dont know...
  9. Y

    libraries for low power design (MSV)

    I do not know of any single tutorial for this purpose. What I did, I designed my own libraries (including level shifters) which were compatible with MSV design. I used the following tools (this flow also adds the level shifters in the netlist automatically after specification in CPF): Cadence...
  10. Y

    libraries for low power design (MSV)

    Look into the liberty (.lib) file. Search for something like "ls*" If there are no level shifters, change the library or design your own level shifter and use that one. Like rca said. Use CPF to specify your level shifter library and supply voltage domains. I personally dont know of a simpler...
  11. Y

    [MOVED] Help with simulating inverter

    Usually people put PMOS on top and NMOS on bottom, but in makes no difference. You do your layout how you feel it should be made. Yes Nwell and Ntub are the same thing. I did not mean that you should change the transistors. I meant that you should change the substrate contacts. In...
  12. Y

    [MOVED] Help with simulating inverter

    I have never gotten that DRC message as far as I can remember, but perhaps if you fix the fundamental errors in your layout the message might dissappear. 1. Change the supply contacts(just interchange the ones you have). Ntap for VDD and Ptap for GND. (You have the opposite i your...
  13. Y

    [SOLVED] Fingers and Multiplier concept in schematic and Layout (CADENCE)

    Fingers: Two poly gates in a single transistor with a source and a drain terminal Multiplier: Two transistors, each with a single poly gate and a source and a drain terminal The setting has an effect on the MOS characteristics. For example the LOD (length of diffusion) effect. This effect will...
  14. Y

    DAC using MiMCap, How to reduce parasitic capacitence

    Hi, I am currently working on an 12bit SAR ADC which includes a SC DAC. Today I started analyzing the effect of top plate capacitance as well. I loose about 20 % (estimated based on the PDK values) of the reference voltage at the output of the DAC due to the capacitive voltage divider effect...
  15. Y

    ASIC library charaacterization

    As I understand it, you are doing simulation characterization based on the models. If you want to do it efficiently, check out the tools I mentioned in my previous post. These tools can use spectre for the simulations, but they will make your life easier by systemizing everything for you.
See more

Part and Inventory Search

Back
Top