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Recent content by yanqele

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    Xilinx FPGA FIFO core

    Re: Xilinx FPGA FIFO core = SOLVED, Thanks to rberek
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    Xilinx FPGA FIFO core

    Thanks again. I begin to understand and as I progress I do find the documentation, unfortunately spread in many places - not easy for somebody who sees that for the first time... May I ask one hopefully last question? I configured the core for a BRAM buffer of width 36 and depth 4096 . The...
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    Xilinx FPGA FIFO core

    Sorry, I made an inattention mistake when I wrote my last mail. I want to build my FIFO using 64kbits out of the 360kbits Block RAM available in my FPGA. Nothing to do with the DDRAM on the development board. Do I correctly understand that I just need to create a clock derived from the system...
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    Xilinx FPGA FIFO core

    I am using a Spartan 3AN development board (Digilent sold by Xilinx). The board has a 32Mx16 bits DDR2 RAM and indeed I see no room for parity on this hardware interface. I understand, am I wrong?, that the Core FIFO generator automatically selects this RAM. My worry and my question came after...
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    Xilinx FPGA FIFO core

    Thanks for answering. I am a physicist. As such I always try to avoid reinventing the wheel. I asked about how to suppress parity because the default FIFO core parametrization yielded an error message for a dangling bit : the parity is thus implemeted (v 4.4). Likewise I asked how to make the...
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    Xilinx FPGA FIFO core

    Newcomer. Can somebody please answer two simple questions? I could not find the answer in docs. The configuration submitted to CoreGen is the most simple one, all defaults, except I need a width of 32 bits and a depth of 4096. The header generated by CoreGen (VHO file) specifies one input...
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