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Recent content by Yanhui

  1. Y

    Cmos level shifter - basic princpal of levl shifter

    Re: Cmos level shifter The power of 1st inv is 1.8v. others 3.6v.
  2. Y

    Temperature response of BGR

    R load too large? Maybe too much voltage consumed at resistor.
  3. Y

    How to increase the gain-BW of a two-stage op-amp?

    pole-splitting compensation/Miller compensation & right-half-plane zero cancellation always used at design.
  4. Y

    Sigma-Delta MOD1: Quantizer gain

    Y(z)=[U(z)-V(z)*z^(-1)]/[1-z^(-1)] if the gain is different Y(z)=[U(z)*gain1-V(z)*z^(-1)*gain2]/[1-z^(-1)] as gain1=gain2=1, u can get the structure of this figure
  5. Y

    extraction problem, need help urgently please

    what is the tool used... maybe a bug of tool :-D u can change the name of pins and try again
  6. Y

    How to implement this transfer function using SC filters?

    SC implemantaion u can use biquad structure to get this BPF TF. See ch9.6 of "CMOS analog circuit design; Phillip E. Allen..."
  7. Y

    Is output noise of 400 uV in bandgap okay?

    Re: noise in bandgap a simulation result? or a test result? the structure, and the source u give, pls~
  8. Y

    question about sc cmfb

    u can use PSS & PAC to get the AC simulation result~
  9. Y

    How to design this Chebyshev filter??

    a pulse source includ all range frequency. after this filter, signal in band will be lose. so, u can get the freq-domain character. the most simply method is get the output data of a 'tran' analysis with a pulse source. sample use the clock frequency. then do FFT analysis to those data after sample.
  10. Y

    How to design this Chebyshev filter??

    It's not a continues circuit! so u cann't use AC analysis. If u have spectre, u can use PSS & PAC to simulate. give a pulse source, get enough tran analysis data. sample and FFT at MATLAB. so u can get the freq-character about this filter.
  11. Y

    how to design delta sigma ADC

    veriloga adc delta sigma I'm also begin a SDM ADC now. Matlab & Spectre are enough, I think. U need to know the z-domain model about SDM at first. And begin from the simplest structure is a good choice. Such as a 2nd Order SDM. We usually realize the z-domain model by switch capacitor...
  12. Y

    PLL Loop filter components

    jitter is discribe of freq-domain phase noise at time domain. they have different units.
  13. Y

    PLL Loop filter components

    To ur 1st question. This paper will helpful if u just do a chargepump PLL design.
  14. Y

    who have tsmc 0.18 lib

    Message is unavailable.

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