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Recent content by xzcv

  1. X

    How to decide delta sigma internal bit

    I have a question I want to design a delta sigma with error feedback architecture that first stage is 2order noise sahping 1bit and two stage is 3order noise shaping 4bit. If input bit are 23bits , how to design internal path bits,for example,how many but should be set at integrator input and...
  2. X

    Which algorithm is simple to implement for a multiplier?

    Re: multiplier how about use carry saving adder to implement?
  3. X

    Problem on sigma-delta modulator design

    if you wnat to get sndr 105db , you should be use 4-order modulator you can reference high-speed high-resolution dac ,1999,march,falakshahi
  4. X

    delta-sigma DAC implemented by VHDL

    vhdl delta sigma is this ip one order delta simga dac?
  5. X

    comparator design flow

    If I want to design a latch comparator,have design flow method?
  6. X

    comparator design flow

    Have anyone can support how to do a comparator design flow? have a method to design or other ways to do? regard thanks
  7. X

    Design a latch comparator consider input voltage

    I have know some thing very appreicate jerryzhao!!
  8. X

    Design a latch comparator consider input voltage

    I have several question for this schematic to deisgn: 1.If I want to design dc 0.9v compare with ramp signal ,the M1 & M2 dc voltage should be set in 0.9v or Vdd/2 initially? 2. the net3 should be set in dc Vdd/2 or other dc level voltage when design? 3. Should be (W/L) of M7 & M9 should be...
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