Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by xv_ning999

  1. X

    clcok domain crossing

    what do your mean for complete documnet
  2. X

    How to do power planning?physical-designers please address.

    Can anyone say something about the content of this ducument?
  3. X

    Schematic Design Tool

    Johnson means to draw the schematic figures not simulation
  4. X

    psyn: phycical compiler advanced

    what is the detail concept of this doc?
  5. X

    Suggest me some DFT Tools

    DFT Tool can anyone tell me which is easier to get or cheaper
  6. X

    Some problems about SCAN Insertion, wlecome to discuss them

    scan insertion Is there anybody can explain relationship between the BSD and Scan chain in synopys tools.Is it better if we multiplex the scan chains to jtag ports,so we can using only one pair of pads for all chains?is this acceptable for testers and ATE equipment
  7. X

    Req. ARM Multiport Memory Controller PL172 code

    why dont u share this source code with us?
  8. X

    about ASIC verification

    the second edition of writing testbenches is not on systemverilog
  9. X

    Suggest me some material/white paper for RAM testing in ASIC

    ASIC RAM testing from what manual did quan digest these pdf ?
  10. X

    how to avoid unknown state during post simulation?

    in my recent design, there were some cross-clockdomain signals.when i was doing post simulation these signals got unknown state due to the hold time violation when they pass through different clock domains. and then these unknown states propagated through my design.They at last make my post...
  11. X

    How to do in place optimization (IPO)?

    How to do IPO? in place optimazation
  12. X

    assignment statement in .vnetlist

    then how to avoid assign statement appearing in our netlist .v file

Part and Inventory Search

Back
Top