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Recent content by xiexie57

  1. X

    Suggest me a good tutorial for Design Vision

    Design Vision ref **broken link removed** Added after 1 minutes: sorry not is. correct link: **broken link removed**
  2. X

    STA constraint for DDR memories

    STA for DDR Paul Zimmer Specializing in: Static Timing using Synopsys PrimeTime Synthesis using Synopsys Design Compiler RTL coding using Verilog Static Timing using IBM Einstimer Physical Design Using Synopsys Astro
  3. X

    How can I convert .db to .v

    But you need,org all db about it TRY read test.db write -format verilog -out test.v
  4. X

    I want to learn VLSI, FPGA and ASIC

    fpga vlsi I love this web in china **broken link removed**
  5. X

    how to practice PERL language

    ref it **broken link removed** for all doc **broken link removed**
  6. X

    TCL Script for Modelsim

    modelsim tcl script simulation add wave Use dos batch vlog -work auto_pre D:/pe61c/ch8.tf vsim -c +nowarnTFMPC +nowarnTSCALE auto_pre.MODULE NAME -do "run -all" -l log_pre/ch8.log
  7. X

    What are the negative setup and hold times?

    setup/hold chek this one "Calculating the setup and hold times at the pins of a chip": h**p://www.arl.wustl.edu/~jaf/hardware/chip-setup-hold-time-calculation.html
  8. X

    Description of Synchronous RAM

    RAM Architecture of FPGAs and CPLDs: A Tutorial **broken link removed** ISE 6 In-Depth Tutorial **broken link removed**
  9. X

    Difference between single port and dual port memory

    http download **broken link removed**
  10. X

    DTMF tutorial for Cadence SoC Encounter

    tutorial CIC http://www.cic.org.tw/cic_v13/main.jsp
  11. X

    Cadence CAD tools tutorial for Virtuoso Schematic and Spectre

    cspiceref The following Cadence CAD tools will be used in this tutorial: · Virtuoso Schematic for schematic capture. · Analog Artist (Spectre) for simulation.
  12. X

    synopsys design compiler workshop

    primetime workshop lab Is good for me detal about this % uncompress PT_ISTA2002.03.tar.Z % tar -xvf PT_ISTA2002.03.tar
  13. X

    Any document on verification pls

    Use testbench to verification. search it Writing Testbenches--Functional Verification of HDL Models_2rd.pdf
  14. X

    discrete fourier transform basics

    design for test tutorial material **broken link removed**
  15. X

    Synopsys & Cadence tutorial

    practice users_guide for all you need.
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