Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by wyhgod

  1. W

    Why frac N's phase noise is worse than int N about 10dB?

    Thanks for your advices again. i just use 0.35um BiCMOS to verify some thoughts. i will try what you have told me .
  2. W

    Why frac N's phase noise is worse than int N about 10dB?

    Hi Mazz， Thanks for your advice very much. The technology i use is 0.35um BiCMOS. I use mathcad to model closed loop phase noise. vco frequency is 3390.84MHz , lo frequency is 1695.42MHz,and div2 is in loop. the following noise is simulation result. PFD+CP output noise Frequency OutNoise...
  3. W

    Why frac N's phase noise is worse than int N about 10dB?

    a gps chip, pll provides LO frequency for receiver and PLL is integrated on the chip with receiver.
  4. W

    Why frac N's phase noise is worse than int N about 10dB?

    Thanks very much.you are the first one to reply this post. yes,i use the exact same chip, first i make it lock in integer mode,then i just turn on sigma-delta,and find the phase noise is worse. I am quietly sure that phase detector frequency is the same in both cases! because the locked...
  5. W

    Why frac N's phase noise is worse than int N about 10dB?

    Dear all, I have designed a fractional N synthesizer,and multi-modulus N range is from 64-255.Using 20 bit sigma-delta to implement fractional mode. Power supply for multi-modulus N and sigma-delta are bonding to pad seperately,and are 3.3v. when i test close loop phase noise, i find the phase...
See more

Part and Inventory Search

Back
Top