Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
One quick question about the wavelet shape of CWT and DWT...
Here we go:
I can't really intuitively understand what's the relations between the Shape of the wavelet of CWT and DWT. What should be the correlation between the Wavelet in continuous form (Wavelet function) and the discrete points...
MSP430FG4618 (Texas Instrument) is a new chip and I cannot find any lib for this chip in Proteus.:cry::|
Anyone has any idea about getting the library for this chip??
BTW, if I cannot find it, is it possible to get a similar chip model (lib.) instead?
Thanks,
By saying the signals are dynamic, you are talking about the high-frequency (maybe RF) signal which would effect the circuits in ways like parasitic capasitors, cross talk, etc?
So, is it also the same thing if I define the input source as 0Hz, -10mv to 10mv? If I look at the transient...
Hello guys.
I am a little bit confused with this concept - 'DC Transfer Characteristic'. In fact, I am doing a simple two-stage Op Amp, and up to now all the sizes has been figured out and put them into LTSpice and simulated it.
But I have a specification called Output Voltage Range, which...
Re: Help needed for Digital Design (timing and power analysi
Thank you for your reply. :)
At this moment we do not have Synopsys software for this design, but Cadence RTL Complier and Encounter, Modelsim, etc.
In fact, in the Encounter, we have Timing option and Power options, but I have no...
At this moment I have finished testing my HDL design in simulation and synthesise it in Cadence Encounter RTL Complier. Then I have got the synthesised gate level .v file afterwards, and I simulated it in modelsim.
Also, I walked through a simple place and route in Cadence APR for
created a...
Thank you very much!
I will try it later!:D
But what do you mean by the same type of signal? If my input is sin wave, then my current is sin wave too. Is it what you mean for the same type of signal? So that in this case can I use RMS ?
I have vdd, gnd and vss, and vdd, vss is my dual power supply. At this moment I am doing a filter using several Op Amp in Cadence Virtuoso. What I want to do is to measure the power dissipation for my whole design by measuring the current flowing in vdd in transient analysis and multiplied by...
rpolyh's cap
I am using rpolyh as the resistor used in the layout (Cadence Virtuoso). And I currently find that the resistor has a 'Cap' in the property in the extracted view, but not in the layout view. I think this is the parasitic capacitance generated after extraction. But my question is ...
Sorry guys, I got another silly question.
I try to sweep the value of the component, let's say, the rpolyh from the analoglib. For the rpolyh, we have resistance, width and length. At this moment, I am doing a filter using Op Amp and rpolyh and cpoly, and what I want is to operate a parametric...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
