Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by wjhzhx

  1. W

    delay loop insertion inside cpld (help!!!)

    And another problem is when you use the same CPLD/FPGA but the faster, your CPLD/FPGA mayby not work.
  2. W

    Looking for Synplify 7.3.1.

    Dose anyone have the SymplifyPro7.3X License just only require the host ID?
  3. W

    Methodology: from fpga to asic?

    Altera and Xilinx have the same upgrade path as jetmarc said
  4. W

    Trouble-Free Switching Between Clock

    Please upload again.
  5. W

    Who can tell me what difference of them? (VHDL)

    The process 2 is wrong because it will generate latch, when rd = 1, what is the result ? But I can't understand where is wrong in process 4
  6. W

    xilinx timing constrain problem

    You test this: NET xxx MAXSKEW = 0.5 ns; xxx is your clock which is not drived by bufg.
  7. W

    Can I trust it completely?When pins are auto assigned.

    You should assign the pin according your CPLD's pin connection on the PCB, the software assigns these "INPUT/GLCRn) and the second pin(INPUT/OE2) were 'GND' " is that these pin is not used in your design, it is best to tie them to GND.
  8. W

    AHDL documentation and LCELL info

    The AHDL is like ABEL language, it can get better and more explicit control over the generated logic, but it is too waste time and the simulating is a problem if your design is not simple
  9. W

    I have a problem in a circuit

    Because 74HC series IC is not high impedenc when power is off, so your circuit will not work, change the 74HC541 to TI's correspond 74 series IC, such as 74LVCT541, 74LVT541, 74AHCT541 and 74ABT541.They are support hot swap(when it's power is off, it output pin and input pin are high impedenc)
  10. W

    What Is Better Xilinx VIRTEX 2 Or Altera Stratix ?

    The new device Stratix G series have front high speed SERDES. The Stratix's differential pairs surport more standard but its pin is not flexible than Virtix-II, its differential pairs are fixed as input or outputcan, and Virtex-II's differential pairs can be programmed as input or output.
  11. W

    Link to open IP cores website

    Thank you!
See more

Part and Inventory Search

Back
Top