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Recent content by windknows

  1. windknows

    Effect of series resistor at the gate of current mirror

    hi, i've seen this circuit in a book talking about current-mode design longtime ago if i'm right, the R here is to increase the bandwidth, the pole will change and it also add a zero. you can calculate the small signal transfer func from the input current to the voltage of the M2 gate
  2. windknows

    [SOLVED] simple bias circuit design

    you should move the resistor to the left side..
  3. windknows

    opamp simulation help

    i think it should work, or maybe you can set it to the voltage of the net57. if it still not work, then maybe you should check the bias for these transistors
  4. windknows

    opamp simulation help

    did you try setting Vdc to half the supply instand of zero? the feedback will force the output to follow the input, so if you set the input to zero, the output will also be closed to zero volt, and since this cascode only have limited output swing, the nmos in the cascode won't work anymore..
  5. windknows

    regulated cascode help

    did you check the region of the cascode? (since you have mentioned the output of the aux amp is fine) i still think you have to match the vbias for the I15...
  6. windknows

    regulated cascode help

    both the vbias and I15 are going to set the vgs of the M46. how do you match them? and maybe the value of the L,C should be more larger to set the complex pole/zero couse by the LC to smaller frequency
  7. windknows

    plotting curve between two nodes in Hspice

    in smartspice it can be plot by 'plot v(y) vs v(x)', but i dont know whether hspice can do this
  8. windknows

    op-amp open-loop GBW simulation problems

    for this inverting OPAMP, the feedback factor is Rin/(Rin+Rfb), actually the Vo/Vin=-A*B1/(1+A*B2) A is the gain of your OPAMP, B1=Rfb/(Rin+Rfb), and B2=Rin/(Rin+Rfb) and if you chang the A to A(s) as a one pole system A/(1+s/po), you will see the close loop gain is...
  9. windknows

    op-amp open-loop GBW simulation problems

    i guess what the stb simulation does is for the loop-gain, which will include the feedback factor. so the amplitude response in the bode plot will actually move up or down according the feedback factor, and the unity gain bandwidth changes..
  10. windknows

    gds of a MOSFET in the weak inversion region

    hi, i've tried some simulation (sweep the Vgs for single transistor), and it seems that the Early voltage (just calculated from id/gds)will decrease when in weak inversion, however the gds will increase.
  11. windknows

    Why common-mode gain tends to follow a U-shape curve?

    Common-mode Gain not quite understand what you mean, but 0dB does not means 0V
  12. windknows

    Why common-mode gain tends to follow a U-shape curve?

    Re: Common-mode Gain i dont know how you build the cm testbench, but for the LC lpf method to test the open loop gain, actually there will be a inverse-U shape, i recall this from the book of 'The Designer's Guide to Spice and Spectre' . if you change your opamp to a simple one-pole system...
  13. windknows

    opamp design problem !!

    you have to change it to dB scale, and in the schematic you are simulating the cm gain, better to refer to the textbook..
  14. windknows

    how to got whole PLL bandwidth

    maybe it is better to built the linear model in matlab and check the bode plot

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