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Recent content by will_tp

  1. W

    why vco phase noise reduce drastically when using ldo

    LDO is on chip. And I only do simulation.
  2. W

    why vco phase noise reduce drastically when using ldo

    This is my vco. this structure is sensitive to vdd noise？
  3. W

    why vco phase noise reduce drastically when using ldo

    My vco frequency is 1.3G , phase noise is -130@1MHz using ideal VDD. If using LDO, phase noise is only -117@1MHz. I have check LDO output noise is only 15nv/squar(hz).
  4. W

    a problem about CML frequency divider

    cml divider I use CML divider to generate quadrature signal. Should the input clock to CML be fully differential? A group of digital divider outputs "clk" and "clkb" just is inverse of "clk". If using "clk" and "clkb" as CML input, what problem will be have?
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