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Recent content by wilfwolf

  1. W

    Help me resolve a CCSS code generation problem

    Hi,everyone, I encountered a code generation problem when finished setup library and models. Hereunder is the error report. Can any experienced ccss user give me any instructions? Thank a lot. C -features=tmplife -c -o lib-sparcOS5/Test_Light_1-u/Test_Light_1_funcs.o -I...
  2. W

    suggestion on IC front-end design

    Yes I'm quite familiar with those tools, such as modelsim, NC-verilog,ISE, DC,PT,and so on, but tools can not do anything for you. I believe there are many skills that I need to have, such as from system to algorithm, from algorithm to implementation,and other fundamental knowledge. As to a...
  3. W

    suggestion on IC front-end design

    Hi,everyone, I'm a student to be graduated soon and planning to engaged in IC front-end design. I've leaned digital design and some common EDA tools, but still don't feel confident enough to the coming challenge. If I want to do good job on this field, what knowledge and skills should I have...
  4. W

    need pci-express spec

    pciexpress_base_10a.pdf I need PCI-Express spec, who can give me an address for free downloading. Thx
  5. W

    Writing testbench in verilog or e language?

    I prefer the opinion of take_care00. To block level, verilog can do well, yet to system level of large scale, e is more powerful
  6. W

    what is the backend design flow

    goal of a digital backend design flow For Mentor tools: 1.Physical layout design(IC station,CDS SE,Apolo) 2.parasitic abstracting and delay calculation(Xcalibre) 3.Physical verification and post simulation(calibre)
  7. W

    how interconnect length depends on fanout

    design compiler wire load model A wire load model is a table for estimating the capacitance,resistance and area of a net. It is based on a statistical correlation between net fanout and net length
  8. W

    question about co-simulation between SPW and NC_Verilog.

    I imported Verilog RTL code into spw,and one symbol is generated. then i set up a system,which this symbol is included. i specified the "cds.lib" directory in simulation manager and choose "SPW-NC" as the engine. it works as expected. But if i have two symbol which are generated from...
  9. W

    Writing testbench in verilog or e language?

    I am planning to write a PCMCIA interface testbench. There are two languages I can select, verilog or e, how do I make a decision? Are there any person used both of them before and give me any advices? Thx.
  10. W

    Booting PC from eprom

    read eeprom from pci card Can a CF card be recognized before the OS? Is it necessary to store a mini OS in the CF card?
  11. W

    Compare Altera & xilinx's FPGA

    Compare @ltera & xilinx's FPGA I prefer xilinx
  12. W

    A newbie here.Can somebody please help me :roll:

    I think the first thing you must make sure is what's the real interest of you, hardware or software, for there are too much knowledge to study, too many things you can do
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