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positive skew clock frequency
sometimes Positive Skew can alleviate setup violation caused by long delay.
if setup violation is the main problem you have to fix ,then you can utilize Positive Skew to Improve frequency ,but Positive Skew can put pressure on hold time. hold time problems will...
xilinx fft
I had used Xilinx fft ipcore v3.2 I find that the data sheet is very usefully, it is very easy to understand.
nothng can be more helpful than that.
dsp48 slice numbers is the first factor you should consider, slice number and ram number is also very
important factors.
i think you shoule make the code synthsised in ise tool first and find out how many slices and block rams you need.
To my opinion , span3a is a dream one to implement
video...
how to fix fpga timing
In FPGA design some reason can cause the setup problems. i think the first task is to find out what caused the problem through reads yout sta report. when you find it you can try to fix it as the following way.
1. too many logic levels, this is always caused by deep...
fpga timing problem fixing
ususally there are no holdtime problem in fpga design.
if it happens,it means that the clock of you design is
a totally failure. you have to redesign you clock.
in fact, there are special clock resources in fpga architecture such as dcm and dll in xilinx fpga,dll in...
ofdm + rake
rake tech can't be adopt with ofdm.cause ofdm symbol is transported in parallel,and it makes every subchannel flat, independent signals can't be got.
got a 50% duty is not difficult.
you can use this circuit 2 times, then the original input clock can be multiplied by 4 ,then use a ff to divide it by 2. you can get a 50% duty and multiplied clock at last.
hi ,you can hav a look at this circuit.
you can goto this chinese website to get more information about it.
http://www.eetop.com.cn/bbs/thread-40713-1-1.html
DFF without reset ?
i had looked through the xilinx fpga Libraries Guide
document files,and i find that there are mainly 3 kind of primitives for ffs in xilinx fpga library as following:
ff with asynchronous reset,ff with synchronous reset,
ff without reset.
why the third kind of ff exists...
fpga training + cairo
quote="verilog_work_group"]Can anybody share xilinx training
part I
Introduction
PERIOD Constraints
OFFSET Constraints
FROM:TO Constraints
Modular Design Constraints
PART II
Using PERIOD and OFFSET constraints
PART III
Creating Groups and Using FROM:TO constraints
PART...
sdram fifo arbitrierung
two important points should be take attention to when design such a fifo.
first, output data rate of the fifo should match to input data rate,otherwise, the fifo depth will be finate
as the average input data rate is always bigger than
output data rate.
you can use...
DCM
both of them are the first global clock resource in xilinx fpga.
dcm is used to manage the clock period and phase shift.
bufg is used to nake good clock tree and get better drive capability for big fanout signals.
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