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you are right VVV, the DC gain is not influenced by the feedback network, but the compensation network's gain between its first zero and second zero equals the ratio of the two resistor in the feedback network. consequently, for higher frequency, it's like the feedback who plays the DC gain, as...
hi everyone,
i'm working on a project with vhdl-ams. i'm not very familiar with either vhdl or vhdl-ams, so i need some help.
here is my question:
i have two std_logic_vector which are converted with ADCs and now i want to do some calculations with the detected signals. i need to do tan or...
rockycheng,
u are right. i mistook the bandwidth of compensated converteur with the pole of output stage. i just wanted to give an intuitive view on the reason that the bandwidth Fbw is limited by the switching frequency Fs.
but did u guys ever read the following doc from TI? a part on page 8...
thx VVV.
i came up with an idea that the output stage of the converter works like a lowpass filter which will block the high freq and then gets a dc output. is this right for the limit of the switching freq to bandwidth§
dc/dc compensation network
hi,
i am confused about the relation between the switching freq and the bandwidth of the overall feedback converter. i read in a doc that the bandwidth should be 3 times smaller that the switching freq, how is that?
i made a circuit and found the output voltage of...
schema buck converter
i'm doing a study on the compensation for DC-DC buck converters.
the schema without compensation shown in the attached pic will ocillate as expected. so, some resistors and capacitors were added into the circuit to stabilize the output. in this case, those were R43, C4...
i read some lecture notes from berkeley ee240 about gm/id design methodology. i think i've got the main point of it but i still have a question: is the chart Id/(W/L)~gm/ID is given by the process? if this isn't given, how can we continue the gm/id way to find the dimension of the device?
thx everybody, but can anyone explain a little more about translinear loop?
i found another application using floating current source on google book search.
the opamp is used as a buffer in a mixed-signal circuit. the input stage is composed of two differential pairs (folded-cascode) to achieve high input CM range. my quesiton is about the output stage, i guess PP15 and NP3 are used to avoid the class B output PP14 and NP4 blocked at the same time...
the gain error was around 3%.
i made another test by increasing the Cmin of the charge-scaling subDAC from 1pF to 1nF. the result was good and the gain error decreased to 0.01%. so i guess this means there is a parasitic capacitance in parrallel with the capacitances in the subDAC, am I right...
gain error of dac
i am simulating a MSB voltage scaling and LSB charge scaling dac with spice. the output has a gain error of 5% and offset error of 0. i wonder how come the gain error.
according to the simulation, the MSB voltage-scaling subDAC worked very well, so the problem is within the...
Hi!
I'm working on a DAC project and i need to do a Monte Carlo simulation to test the Device and Lot tolerance of the output when ΔR/R and ΔC/C are given. i made a try and the simulation began though i didn't find the right place to set up the Device and Lot tolerance or how to set up the...
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