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Capacitor
I recently want to test capacitor's stability, and I want to set up a test lab to test this capacitor. any idea how I can do it ? because some of the capacitor aging almost 80% . but in the datasheet it said it age a little bit.
what things make capacitor aging that quickly ...
capacitor aging part 2
To all:
Thank you for everyone who contribute your knowledge to it.
According to asoon recommanded website, it says that film capacitors is aging only 1% for its life time.
But one of my capacitor is aging 10-20 percents, and it is Metallized Polyester
Film...
capacitor in series
For example, I have 2 capacitors , these two cap are in series, capacitance will be
(C1+C2)/2, what about working voltage ? and break down voltage ? The working voltage for both capacitors are the same. let's say it is 10V.
Thank you
Re: capacitor aging
do you know where to get information about aging in each type of capacitor, how the capacitance is changed by time. the one I am most interested is matallized polyester film capacitor, which does aging a little, but in reality, it is not quite ture.
bsim3v3 49 model berkeley
I am trying to calculate the Id value by the equation
"Id = 1/2 * u0 * cox * (Vgs -Vt)^2 * (1 + lambda * Vds) and the Bsim Model
please guide me throught the calculation , thanks
just for understanding purpose , let's assume Vgs = 1 , Vds = 1.
.MODEL CMOSN NMOS (...
Please see the attachment for more detail about the circuit and problem.
I believe I use 1.6 micro technology (spice model from University).
Here is the spice model for nmos and pmos transistor :
simulator lang=spice
.model nmos nmos
+ level=1 vto=1 kp=16u gamma=1.3 lambda=0.01
+ phi=0.7...
To Analog IC helper :
I recently design OP-AMP , and got very big issue with current mirror in OP-AMP circuit. Please download the circuit ( that is attachment) , Within the white square, that is the simple current mirror to provider current for different AMP (1st stage) .
My...
I have done the dc analysis . I believe 1.6 is the technology I use . because I can not go lower than 1.61 in W and L , if I key in lower or equal to 1.6 , the simulator will show the error.
The model files I use for the simulation as below
simulator lang=spice
.model nmos nmos
+ level=1...
I repeat the simulation with bigger than 1.61u , then the id is droping so quickly !!
when I set both Width and length are 2u , then id value is 80u .... I don't quite understand why this is happening like that . !! Please help me to understand.
design of rsds circuit
I recently need to design RSDS circuit , and would like to know where I can get information from. And how do I get start in circuit creation.
I just know RSDS a little , and just wonder RSDS reciever is created by OP-AMP or differential Amp.
please correct me if I am...
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