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LvW, I mean that in good design conversion of negative feedback to positive feedback is not critical, like in poor design. And one can say that neg. feedback don't turns into pos. if it will not cause problems.
But if we will operate in strictly terms - yes, every neg. feedback turns into pos.
Gain of opamp decrease when frequency increase. And phase shift increase when frequency increase.
When gain decreace to value 1 (0 dB) you should have a phase margin, otherwise when you use your opamp with negative feedback it can turns in positive.
Phase margin define as 180 degreess minus...
At higher frequencies phase shift can become 180 degrees and negative feedback will turn positive. Therefore opams require phase margin. It's mean when gain of operational amplifier lower to 0 dB phase shift should be (180 deg. - "phase margin").
So, not every negative feedback converts to...
erikl, can you explain clearly?
I don't understand why there are 454 mV in DC specs and 540 mV in AC specs. If I use in testbench of driver 100 Ohm res and capacitance load (receiver give only additional cap load) I would never get AC Vohd larger than DC Vold, only smaller (depend on cap...
Hello,
In the RapidIO standard DC specs for Driver is similar to TIA-644-A standard (Vohd = 247...454 mV, Vold = -454...-247 mV).
But AC specs are:
Vohd = 200...540 mV,
Vold = -540...-200 mV.
What from appear this specs? Does it appear on acount of reflections in transmission line?
What is...
noise in miller opamp
1) Yes, it still used. All depend on for what you will use your opamp.
2) It's not preferred to be pmos. If input signal changes from 0 to x*VDD, where 0<x<1, it must be pmos. If input signal changes from x*VDD to VDD input transistors must be nmos. Otherwise it will not...
LVDS driver question
Thank you for explain question about transmission line.
And what about output capacitance of driver (ESD, PAD etc.)? Why it is not include in CL?
LVDS driver question
Hi! I'm designing LVDS driver and I have a question: how simulate it correctly? =) I mean what is adequate model of load? Image in the attachment is the schematic of my testbench.
Questions:
1. Is it correct? Should I take into account transmission line, inductance...
lvds driver topology
Hi! I'm design LVDS driver. I want to understand what load should i place at driver outputs when I simulate it.
Can somebody advise topology of testbench? Does testbench include something like tline from analogLib or it's consist only of RC?
start up circuit
I designed Bandgap voltage reference and startup circuit for it. I have read topics about BGVR and startup. I verify startup this way: make Vdd constant value (or use vpwl source and ramp on Vdd), set initial conditions for nodes and make transient simulation.
Vref reaches...
psrr and bandgap
I had improve my Bandgap. PSRR plot in attachment.
I have some questions.
1) Should PSRR be more smooth?
2) Now PSRR at low frequencies are good. But what about high frequencies? How much should be PSRR at 10 Mhz, at 100 Mhz? In papers I have seen all PSRR plots was from 1...
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