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i really really agree with Teddy. when simulating, the important thing is not the simlation tools but the model you get. the result IC chip work well or not depend on the accuracy of the model.
Hi, DenisMark . we design this ref in a boost circuit. The output of the SMPS provide power supply to the control IC. now I post the simulation results of the ref which I add some pulse at vssa to replace the gnd with bonding. The simulation results are as following:
this is the ref output, the...
there are so many intelligent professor in universities and un-known engeneers who contribute a lot to the development of the analog IC design. they all should be respected by us.
last night i checked the simulation results carefully and found it seemed the BGR oscilates at very high frequency about 500Mhz, as like the figure posted by hktk. it is almost the same if u remove the capacitor C3, i think it is because the C3 compensates the circuit at low frequency, the...
thank u, DenisMark,i will try the method u mentioned.
Added after 4 hours 47 minutes:
hi,DenisMark. i think the proper breaking point is the output node of OPAMP or the Positive input node of OPAMP, but the previous break method is hard to estimate the load effect. the dc gain of the two...
hi, DenisMark. the VDDA has a ripple of 30mv, and if without bonding, the noutput of BGR is OK.so i think the bad transient due to the VSSA with bonding. the most probable reason is the loop stability. where and how to break the loop? how to estimate the load effect?
T. Y. Li and J. A. Yorke, “Period three implies chaos,” Am. Math. Monthly, vol. 82, no. 10, pp. 985-992, 1975.
i have spend a lot of time searching in google but i can't get the original paper.
if u have this paper, please email me. my email adress is li.yanlin@hotmail.com.
degeneration matching current source
i think dipswitch is right. in bjt case, the resistor connect the emitter is for reduce the mismatch of Is and in mos case, it has not this improvement. for both case, it can incraese the output resistance.
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