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The ISE will do some optimisation and possiblely reduce you design to < 100%.
If it can't, the tool will tell.
Anyway, you won't get your timing closure for that kind of resource utilization.
port array in vhdl
In VHDL, you can use 2D array in the port.
Just manually expend them into 1D array.
To use it internally, I think it is OK with ISE.
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