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Dear all
I am working for the first time on timing closure probs. I have a very strange values generated . i am using a freq of 1.25 ns .
and wen i see the slack report post placed it shows me a +ve slack of 2+ i am confused abt this values. the slack valus is more then the freq. i am using...
we generally estimate the these values based on the prev. tech and projects. else according to me its should be a just trail error method . but just keep in mind ur freq. and tech.
vlsi stud
Hello every one
I used synopsys DC for synthesis with the option of clock gating .. now i want use model sim for gatel level netlist simulation. can some one please tell as how to proceed .. r please give soem materials which gives info abt this ..
thnks a lot in advacne
sing
Re: INFINEON
hello Salma
. i tried searching for general analog interview question but could not find proper one. can u please sugget me soem sites r books which deal with analog and mixed sigals design.
thnks in advance
antonio
INFINEON
Hello Salma
thanks again for ur prompt response . i now got some idea wat kind of questions I can expect . I will definatly let you know once every thng is over.
antony
INFINEON
Hello every one,
i am a fresh VLSI graduate and am called for an interview with INFINEON italy. the general procedure has 3 rounds
1) general test
2) tech test
3) interview
if any one has already appeared for this interview, please let me know with some possible questions as...
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