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Recent content by vlsi_maniac

  1. V

    why karnaugh maps use gray code booleans

    why karnaugh maps use gray code booleans thanks
  2. V

    [SOLVED] How to do sampling in VHDL (ADC)?

    Can anyone comment on the attached PDF from Lattice Semi. They have implemented an ADC inside FPGA. How do we write a Verilog Code for such stuff ?
  3. V

    How to calculate minimum frequency of a logic

    Well it an interview question....!
  4. V

    how to calculate comb.delay btwn input pad and register

    hi, i was using synplify tool and i was stuck with a doubt. i have a comb path between input pad and a reg which is output. input is not registered. how to calculate the combinational path delay. how to calculate the same in synopsys design compiler.what command i need to give
  5. V

    How to calculate minimum frequency of a logic

    hi, there is method to calculate maximum frequency of a logic(between two regs) but is there any method by which we can able to calculate minimum frequency of a logic. help needed.
  6. V

    Need to generate pulse from input counter value no clock

    hi,i am need to generate a pulse from input value i get. example - i get a value of 6 then i have to generate a pulse high for 6ns. (timescale 1ns) no clock is to be used in the logic. the working is on hash delays. but how to use the number in the input as hash delay and generate a pulse high...
  7. V

    In DC set_ip_delay or set_op_delay who & how decides val

    hi all, while going through a tutorial on DC i got one doubt. create_clock constraints clock to a frequency that design has to work. but if we put set_input_delay who decides these factors. since set_input_delay indicates time from input pad to input of FF on what factors we should decide these...
  8. V

    gate level simulation- sdf file how to read clk & reset

    hi i was trying to do gate level simulation using quartus and modelsim. the dut is a counter and it works at 411 MHz. now if i write the test bench am i supposed to generate the clock in testbench not more than 411MHz. and i have seen in sdo file the below para (CELL (CELLTYPE...
  9. V

    asic-world interview question

    hi all, i have a doubt regarding the below question. Q : Referring to the diagram below, briefly explain what will happen if the propagation delay of the clock signal in path B is much too high compared to path A. How do we solve this problem if the propagation delay in path B can not be reduced...
  10. V

    doubt in digitaldesign(morrismano) setup time description

    hi,this is regarding edge triggered ff setup time described in morris mano. it says that D input must be maintained constant prior to the application of pulse and if it changes with pulse at zero the output of nand gates (1 & 4) changes. but what is the issue with the statement - though the...
  11. V

    gate level simulation going wrong for counter DUT

    i am new to gate level simulation. i am using altera quartus and modelsim. i have done place & route,generated sdo & vo files. my DUT is a simple counter and works at 260MHz targeted at stratix. now how should i decide how much time i should apply reset to the DUT (i have applies for a period of...
  12. V

    interview question on setup...please solve

    can you please tell how you got 12ns thanks
  13. V

    interview question.combinational circuit frequency division

    1)Design a simple circuit based on combinational logic to double the output frequency 2)Design a COMBINATIONAL circuit that can divide the clock frequency by 2. thanks
  14. V

    interview question on setup...please solve

    hi all, 1)Convert D-latch into divider by 2. 2)What is the max clock frequency the circuit can handle ? T_setup= 6nS T_hold = 2nS T_propagation = 10nS thanks
  15. V

    what does divide by 3 counter mean?

    hi,what does divide by 3 counter mean i have clock of 10ns then what does divide by 3 ? thanks
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